/** * \brief Test backup mode. * * \note To test backup mode, the program must run out of flash. */ static void test_backup_mode(void) { puts(STRING_BACKUP); /* Wait for the transmission done before changing clock */ while (!uart_is_tx_empty(CONSOLE_UART)) { } /* GPBR0 is for recording times of entering into backup mode */ gpbr_write(GPBR0, gpbr_read(GPBR0) + 1); /* Enable the PIO for wake-up */ example_set_wakeup_from_backup_mode(); /* Switch MCK to slow clock */ pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); /* Disable unused clock to save power */ pmc_osc_disable_xtal(0); example_disable_pll(); /* Enter into backup mode */ pmc_enable_backupmode(); /* Note: The core will reset when exiting from backup mode. */ }
/** * \brief Test wait mode. */ static void test_wait_mode(void) { puts(STRING_WAIT); #if SAMG55 /* Wait for the transmission done before changing clock */ while (!usart_is_tx_empty(CONSOLE_UART)) { } #else /* Wait for the transmission done before changing clock */ while (!uart_is_tx_empty(CONSOLE_UART)) { } #endif /* Configure fast RC oscillator */ pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); #if (SAMG) pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); #else pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); #endif pmc_switch_mck_to_mainck(PMC_PCK_PRES_CLK_1); #if (SAMG) g_ul_current_mck = 8000000; /* 8MHz */ #else g_ul_current_mck = 4000000; /* 4MHz */ #endif /* Disable unused clock to save power */ pmc_osc_disable_xtal(0); example_disable_pll(); /* Set wakeup input for fast startup */ example_set_wakeup_from_wait_mode(); /* Enter into wait Mode */ pmc_enable_waitmode(); /* Set default clock and re-configure UART */ set_default_working_clock(); reconfigure_console(g_ul_current_mck, CONF_UART_BAUDRATE); puts("Exit from wait Mode.\r"); }
/** * Save clock settings and shutdown PLLs */ __always_inline static void pmc_save_clock_settings( uint32_t *p_osc_setting, uint32_t *p_pll0_setting, uint32_t *p_pll1_setting, uint32_t *p_mck_setting) { if (p_osc_setting) { *p_osc_setting = PMC->CKGR_MOR; } if (p_pll0_setting) { *p_pll0_setting = PMC->CKGR_PLLAR; } if (p_pll1_setting) { #if (SAM3S || SAM4S) *p_pll1_setting = PMC->CKGR_PLLBR; #elif (SAM3U || SAM3XA) *p_pll1_setting = PMC->CKGR_UCKR; #else *p_pll1_setting = 0; #endif } if (p_mck_setting) { *p_mck_setting = PMC->PMC_MCKR; } /* Switch MCK to internal 4/8/12M RC for fast wakeup and disable unused clock for power saving. */ pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); pmc_osc_disable_xtal(0); pmc_disable_pllack(); #if (SAM3S || SAM4S) pmc_disable_pllbck(); #elif (SAM3U || SAM3XA) pmc_disable_upll_clock(); #endif pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1); }
/** * \brief Change clock configuration. * * \param p_uc_str Hint string to be output on console before changing clock. */ static void user_change_clock(uint8_t *p_uc_str) { uint8_t uc_key; uint32_t ul_id; /* Print menu */ puts(CLOCK_LIST_MENU); while (uart_read(CONSOLE_UART, &uc_key)) { } printf("Select option is: %c\n\r\n\r", uc_key); if (p_uc_str) { puts((char const *)p_uc_str); } while (!uart_is_tx_empty(CONSOLE_UART)) { } if ((uc_key >= MIN_CLOCK_FAST_RC_ITEM) && (uc_key <= MAX_CLOCK_FAST_RC_ITEM)) { ul_id = uc_key - MIN_CLOCK_FAST_RC_ITEM; /* Save current clock */ g_ul_current_mck = g_fastrc_clock_list[ul_id][0]; /* Switch MCK to Slow clock */ pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); /* Switch mainck to fast RC */ pmc_osc_enable_fastrc(CKGR_MOR_MOSCRCF_8_MHz); pmc_switch_mainck_to_fastrc(g_fastrc_clock_list[ul_id][1]); /* Switch MCK to mainck */ pmc_switch_mck_to_mainck(g_fastrc_clock_list[ul_id][2]); /* Disable unused clock to save power */ pmc_osc_disable_xtal(0); example_disable_pll(); } else if ((uc_key >= MIN_CLOCK_PLL_ITEM) && (uc_key <= MAX_CLOCK_PLL_ITEM)) { ul_id = uc_key - MIN_CLOCK_PLL_ITEM; /* Save current clock */ g_ul_current_mck = g_pll_clock_list[ul_id][0]; #if (SAMG) /* Switch MCK to main clock */ pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1); #else /* Switch MCK to slow clock */ pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); /* Switch mainck to external xtal */ pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US); #endif /* Configure PLL and switch clock */ example_switch_clock(g_pll_clock_list[ul_id][1], PLL_COUNT, g_pll_clock_list[ul_id][2], g_pll_clock_list[ul_id][3]); #if (!SAMG) /* Disable unused clock to save power */ pmc_osc_disable_fastrc(); #endif } else { puts("Clock is not changed.\r"); } }
static unsigned long wait_mode_power_down_hook( unsigned long delay_ms ) { bool jtag_enabled = ( ( CoreDebug ->DHCSR & CoreDebug_DEMCR_TRCENA_Msk ) != 0 ) ? true : false; bool jtag_delay_elapsed = ( mico_get_time() > JTAG_DEBUG_SLEEP_DELAY_MS ) ? true : false; uint32_t elapsed_cycles = 0; /* Criteria to enter WAIT mode * 1. Clock needed counter is 0 and no JTAG debugging * 2. Clock needed counter is 0, in JTAG debugging session, and MiCO system tick has progressed over 3 seconds. * This is to give OpenOCD enough time to poke the JTAG tap before the CPU enters WAIT mode. */ if ( ( samg5x_clock_needed_counter == 0 ) && ( ( jtag_enabled == false ) || ( ( jtag_enabled == true ) && ( jtag_delay_elapsed == true ) ) ) ) { uint32_t total_sleep_cycles; uint32_t total_delay_cycles; /* Start real-time timer */ rtt_init( RTT, RTT_CLOCK_PRESCALER ); /* Start atomic operation */ DISABLE_INTERRUPTS; /* Ensure deep sleep bit is enabled, otherwise system doesn't go into deep sleep */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Disable SysTick */ SysTick->CTRL &= ( ~( SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk ) ); /* End atomic operation */ ENABLE_INTERRUPTS; /* Expected total time CPU executing in this function (including WAIT mode time) */ total_sleep_cycles = MS_TO_CYCLES( delay_ms ); /* Total cycles in WAIT mode loop */ total_delay_cycles = ( total_sleep_cycles / RTT_MAX_CYCLES + 1 ) * RC_OSC_DELAY_CYCLES + WAIT_MODE_ENTER_DELAY_CYCLES + WAIT_MODE_EXIT_DELAY_CYCLES; if ( total_sleep_cycles > total_delay_cycles ) { /* Adjust total sleep cycle to exclude exit delay */ total_sleep_cycles -= WAIT_MODE_EXIT_DELAY_CYCLES; /* Prepare platform specific settings before entering powersave */ // platform_enter_powersave(); ///* Prepare WLAN bus before entering powersave */ //platform_bus_enter_powersave(); /* Disable brownout detector */ supc_disable_brownout_detector( SUPC ); /* Backup system I/0 functions and set all to GPIO to save power */ system_io_backup_value = matrix_get_system_io(); matrix_set_system_io( 0x0CF0 ); /* Switch Master Clock to Main Clock (internal fast RC oscillator) */ pmc_switch_mck_to_mainck( PMC_PCK_PRES_CLK_1 ); /* Switch on internal fast RC oscillator, switch Main Clock source to internal fast RC oscillator and disables external fast crystal */ pmc_switch_mainck_to_fastrc( CKGR_MOR_MOSCRCF_8_MHz ); /* Disable external fast crystal */ pmc_osc_disable_xtal( 0 ); /* Disable PLLA */ pmc_disable_pllack( ); /* This above process introduces certain delay. Add delay to the elapsed cycles */ elapsed_cycles += rtt_read_timer_value( RTT ); while ( wake_up_interrupt_triggered == false && elapsed_cycles < total_sleep_cycles ) { uint32_t current_sleep_cycles = total_sleep_cycles - elapsed_cycles; /* Start real-time timer and alarm */ rtt_init( RTT, RTT_CLOCK_PRESCALER ); rtt_write_alarm_time( RTT, ( current_sleep_cycles > RTT_MAX_CYCLES ) ? RTT_MAX_CYCLES - RC_OSC_DELAY_CYCLES : current_sleep_cycles - RC_OSC_DELAY_CYCLES ); __asm("wfi"); /* Enter WAIT mode */ //pmc_enable_waitmode(); /* Clear wake-up status */ rtt_get_status( RTT ); /* Add sleep time to the elapsed cycles */ elapsed_cycles += rtt_read_timer_value( RTT ); } /* Re-enable real-time timer to time clock reinitialisation delay */ rtt_init( RTT, RTT_CLOCK_PRESCALER ); /* Reinit fast clock. This takes ~19ms, but the timing has been compensated */ init_clocks(); /* Disable unused clock to save power */ pmc_osc_disable_fastrc(); /* Restore system I/O pins */ matrix_set_system_io( system_io_backup_value ); /* Restore WLAN bus */ //platform_bus_exit_powersave(); // /* Restore platform-specific settings */ // platform_exit_powersave(); /* Add clock reinitialisation delay to elapsed cycles */ elapsed_cycles += rtt_read_timer_value( RTT ); /* Disable RTT to save power */ RTT->RTT_MR = (uint32_t)( 1 << 20 ); } } /* Start atomic operation */ DISABLE_INTERRUPTS; /* Switch SysTick back on */ SysTick->CTRL |= ( SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk ); /* Clear flag indicating interrupt triggered by wake up pin */ wake_up_interrupt_triggered = false; /* End atomic operation */ ENABLE_INTERRUPTS; /* Return total time in milliseconds */ return CYCLES_TO_MS( elapsed_cycles ); }