static int pmc_dev_state_show(struct seq_file *s, void *unused) { struct pmc_dev *pmc = s->private; u32 func_dis, func_dis_2, func_dis_index; u32 d3_sts_0, d3_sts_1, d3_sts_index; int dev_num, dev_index, reg_index; func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS); func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2); d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0); d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1); dev_num = ARRAY_SIZE(dev_map); for (dev_index = 0; dev_index < dev_num; dev_index++) { reg_index = dev_index / PMC_REG_BIT_WIDTH; if (reg_index) { func_dis_index = func_dis_2; d3_sts_index = d3_sts_1; } else { func_dis_index = func_dis; d3_sts_index = d3_sts_0; } seq_printf(s, "Dev: %-32s\tState: %s [%s]\n", dev_map[dev_index].name, dev_map[dev_index].bit_mask & func_dis_index ? "Disabled" : "Enabled ", dev_map[dev_index].bit_mask & d3_sts_index ? "D3" : "D0"); } return 0; }
static int pmc_sleep_tmr_show(struct seq_file *s, void *unused) { struct pmc_dev *pmc = s->private; u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr; s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT; s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT; s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT; s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT; s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT; seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr); seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr); seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr); seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr); seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr); return 0; }
static int pmc_pss_state_show(struct seq_file *s, void *unused) { struct pmc_dev *pmc = s->private; u32 pss = pmc_reg_read(pmc, PMC_PSS); int pss_index; for (pss_index = 0; pss_index < ARRAY_SIZE(pss_map); pss_index++) { seq_printf(s, "Island: %-32s\tState: %s\n", pss_map[pss_index].name, pss_map[pss_index].bit_mask & pss ? "Off" : "On"); } return 0; }