static int s5pc210_phy_control(int on)
{
int ret = 0;
u32 val = 0;
struct pmic *p = get_pmic();
if (pmic_probe(p))
return -1;
if (on) {
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_ON);
ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
} else {
ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
ENSAFEOUT1, LDO_OFF);
}
if (ret) {
puts("MAX8997 LDO setting error!\n");
return -1;
}
return 0;
}
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg, rev_id;
ret = power_pfuze3000_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("PFUZE3000");
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
/* disable Low Power Mode during standby mode */
pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
reg |= 0x1;
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
return 0;
}
void power_init(void)
{
unsigned int val;
struct pmic *p;
pmic_init();
p = get_pmic();
/* Set VDDA to 1.25V */
pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_25;
pmic_reg_write(p, REG_SW_2, val);
/*
* Need increase VCC and VDDA to 1.3V
* according to MX53 IC TO2 datasheet.
*/
if (is_soc_rev(CHIP_REV_2_0) == 0) {
/* Set VCC to 1.3V for TO2 */
pmic_reg_read(p, REG_SW_1, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
pmic_reg_write(p, REG_SW_1, val);
/* Set VDDA to 1.3V for TO2 */
pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
pmic_reg_write(p, REG_SW_2, val);
}
}
void ldo_mode_set(int ldo_bypass)
{
unsigned int value;
u32 vddarm;
struct pmic *p = pfuze;
if (!p) {
printf("No PMIC found!\n");
return;
}
/* switch to ldo_bypass mode */
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM to 1.275V */
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
value &= ~0x1f;
value |= PFUZE300_SW1AB_SETP(1275);
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
set_anatop_bypass(1);
vddarm = PFUZE300_SW1AB_SETP(1175);
pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
value &= ~0x1f;
value |= vddarm;
pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
finish_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
void ldo_mode_set(int ldo_bypass)
{
unsigned int value;
struct pmic *p = pfuze;
if (!p) {
printf("No PMIC found!\n");
return;
}
/* switch to ldo_bypass mode */
if (ldo_bypass) {
/* decrease VDDARM to 1.15V */
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
value &= ~0x3f;
value |= PFUZE100_SW1ABC_SETP(11500);
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
/* decrease VDDSOC to 1.15V */
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
value &= ~0x3f;
value |= PFUZE100_SW1ABC_SETP(11500);
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
set_anatop_bypass(1);
printf("switch to ldo_bypass mode!\n");
}
}
void pmic_88pm886_base_init(struct pmic *p_base)
{
u32 data;
/* disable watchdog */
pmic_update_bits(p_base, 0x1d, (1 << 0), (1 << 0));
/*----following setting is for Audio Codec ---*/
/* enable 32Khz low jitter XO_LJ = 1 */
pmic_update_bits(p_base, 0x21, (1 << 5), (1 << 5));
/* enable USE_XO = 1 */
pmic_update_bits(p_base, 0xd0, (1 << 7), (1 << 7));
/* output 32k from XO */
pmic_update_bits(p_base, 0xe2, 0xf, 0xa);
/* read-clear interruption registers */
pmic_reg_read(p_base, PM886_REG_INT1, &data);
pmic_reg_read(p_base, PM886_REG_INT2, &data);
pmic_reg_read(p_base, PM886_REG_INT3, &data);
pmic_reg_read(p_base, PM886_REG_INT4, &data);
/*
* print out power up/down log and save in memory
* the power up log has little change vesus to
* 88pm820/88pm860
*/
get_powerup_down_log(g_chip);
}
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
int tim, i = 0;
struct pmic *p = pmic_get("FSL_PMIC");
int ret;
if (!p)
return -1;
do {
ret = pmic_reg_read(p, REG_RTC_DAY, &day1);
if (ret < 0)
return -1;
ret = pmic_reg_read(p, REG_RTC_TIME, &time);
if (ret < 0)
return -1;
ret = pmic_reg_read(p, REG_RTC_DAY, &day2);
if (ret < 0)
return -1;
} while (day1 != day2 && i++ < 3);
tim = day1 * 86400 + time;
rtc_to_tm(tim, rtc);
rtc->tm_yday = 0;
rtc->tm_isdst = 0;
return 0;
}
int power_init_board(void)
{
struct pmic *p;
unsigned int reg, ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
ret = pfuze_mode_init(p, APS_PFM);
if (ret < 0)
return ret;
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
return 0;
}
static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
{
int val;
struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
struct pfuze100_regulator_desc *desc = plat->desc;
if (op == PMIC_OP_GET) {
if (desc->type == REGULATOR_TYPE_BUCK) {
if (!strcmp(dev->name, "swbst")) {
val = pmic_reg_read(dev->parent,
desc->vsel_reg);
if (val < 0)
return val;
val &= SWBST_MODE_MASK;
val >>= SWBST_MODE_SHIFT;
*opmode = val;
return 0;
}
val = pmic_reg_read(dev->parent,
desc->vsel_reg +
PFUZE100_MODE_OFFSET);
if (val < 0)
return val;
val &= SW_MODE_MASK;
val >>= SW_MODE_SHIFT;
*opmode = val;
return 0;
} else if (desc->type == REGULATOR_TYPE_LDO) {
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
u32 reg;
int ret;
power_pfuze100_init(1);
p = pmic_get("PFUZE100");
if (!p)
return -EINVAL;
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, ®);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set SWBST to 5.0V and enable (for USB) */
pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
return 0;
}
void pmic_88pm880_base_init(struct pmic *p_base)
{
u32 data;
/* disable watchdog */
pmic_update_bits(p_base, PM880_REG_WDOG, PM880_REG_WDOG_DIS, PM880_REG_WDOG_DIS);
/*----following setting is for Audio Codec ---*/
/* enable 32Khz low jitter XO_LJ = 1 */
pmic_update_bits(p_base, PM880_REG_LOWPOWER2, PM880_REG_XO_LJ, PM880_REG_XO_LJ);
/* enable USE_XO = 1 */
pmic_update_bits(p_base, PM880_REG_RTC_CTRL1, PM880_REG_USE_XO, PM880_REG_USE_XO);
/* output 32k from XO */
pmic_update_bits(p_base, PM880_REG_AON_CTRL2, PM880_CLK32K2_SEL_MASK, PM880_CLK32K2_SEL_32);
/* read-clear interruption registers */
pmic_reg_read(p_base, PM880_REG_INT1, &data);
pmic_reg_read(p_base, PM880_REG_INT2, &data);
pmic_reg_read(p_base, PM880_REG_INT3, &data);
pmic_reg_read(p_base, PM880_REG_INT4, &data);
/* turn on cfd clock, so we could turn off CFD_PLS_EN later */
pmic_update_bits(p_base, PM880_REG_CLK_CTRL_1, PM880_CFD_CLK_EN, PM880_CFD_CLK_EN);
/*
* print out power up/down log and save in memory
* the power up log has little change vesus to
* 88pm820/88pm860/88pm880
*/
get_powerup_down_log(g_chip);
}
void exynos_lcd_power_on(void)
{
struct udevice *dev;
int ret;
u8 reg;
ret = pmic_get("max8998-pmic", &dev);
if (ret) {
puts("Failed to get MAX8998!\n");
return;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
reg |= MAX8998_LDO17;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
reg |= MAX8998_LDO7;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return;
}
}
static int pmic_clk_enable(struct clk_hw *hw)
{
struct pmic_clk *clk_pmic = container_of(hw, struct pmic_clk, hw);
u32 reg_val = 0;
unsigned long rfclk_flag = 0;
spin_lock_irqsave(&g_pmic_xoinfo.xorf_lock, rfclk_flag);
/* 打开前写0 */
pmic_reg_read(clk_pmic->freq_addr_offset, ®_val);
reg_val &= (~(clk_pmic->freq_mask));
pmic_reg_write(clk_pmic->freq_addr_offset, reg_val);
/*enable clk*/
pmic_mutli_core_lock();
pmic_reg_read(clk_pmic->en_dis_offset, ®_val);
reg_val |= (((u32)0x1) << clk_pmic->en_dis_bit);
pmic_reg_write(clk_pmic->en_dis_offset, reg_val);
pmic_mutli_core_unlock();
/*delay 6us*/
udelay(clk_pmic->delay_us);
/* 打开后写1 */
pmic_reg_read(clk_pmic->freq_addr_offset, ®_val);
reg_val |= clk_pmic->freq_mask;
pmic_reg_write(clk_pmic->freq_addr_offset, reg_val);
spin_unlock_irqrestore(&g_pmic_xoinfo.xorf_lock, rfclk_flag);
return 0;
}
static int power_init(void)
{
unsigned int val;
int ret = -1;
struct pmic *p;
if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
pmic_dialog_init();
p = get_pmic();
/* Set VDDA to 1.25V */
val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
val |= DA9052_SUPPLY_VBCOREGO;
ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
/* Set Vcc peripheral to 1.30V */
ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
}
if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
pmic_init();
p = get_pmic();
/* Set VDDGP to 1.25V for 1GHz on SW1 */
pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
ret = pmic_reg_write(p, REG_SW_0, val);
/* Set VCC as 1.30V on SW2 */
pmic_reg_read(p, REG_SW_1, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
ret |= pmic_reg_write(p, REG_SW_1, val);
/* Set global reset timer to 4s */
pmic_reg_read(p, REG_POWER_CTL2, &val);
val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
/* Set VUSBSEL and VUSBEN for USB PHY supply*/
pmic_reg_read(p, REG_MODE_0, &val);
val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
ret |= pmic_reg_write(p, REG_MODE_0, val);
/* Set SWBST to 5V in auto mode */
val = SWBST_AUTO;
ret |= pmic_reg_write(p, SWBST_CTRL, val);
}
return ret;
}
void board_pmic_power_fixup(struct pmic *p_power)
{
u32 val;
/* Set VCC_main(buck1) as 1.2v*/
val = 0x30;
pmic_reg_write(p_power, 0x3c, val);
pmic_reg_write(p_power, 0x3d, val);
pmic_reg_write(p_power, 0x3e, val);
pmic_reg_write(p_power, 0x3f, val);
/* Set buck4 as 1.8V */
val = 0x54;
pmic_reg_write(p_power, 0x42, val);
pmic_reg_write(p_power, 0x43, val);
pmic_reg_write(p_power, 0x44, val);
pmic_reg_write(p_power, 0x45, val);
/* Set buck1 ramp up speed to 12.5mV/us */
pmic_reg_read(p_power, 0x78, &val);
val &= ~(7 << 3);
val |= (0x6 << 3);
pmic_reg_write(p_power, 0x78, val);
/* Set buck1 audio mode as 0.8V */
val = 0x10;
pmic_reg_write(p_power, 0x38, val);
/* enable buck1 sleep modewhen SLEEpn = '0' */
pmic_reg_read(p_power, 0x5a, &val);
val &= 0xfc;
val |= 0x2;
pmic_reg_write(p_power, 0x5a, val);
/* Set LDO8 as 3.1V for LCD */
marvell88pm_set_ldo_vol(p_power, 8, 3100000);
/* Set LDO12 as 3.0V for SD IO/bus */
marvell88pm_set_ldo_vol(p_power, 12, 3000000);
/* Set LDO13 as 3.0V for SD Card */
marvell88pm_set_ldo_vol(p_power, 13, 3000000);
/* Set LDO14 as 3.0V for eMMC */
marvell88pm_set_ldo_vol(p_power, 14, 3000000);
/* Set LDO15 as 1.8V for LCD */
marvell88pm_set_ldo_vol(p_power, 15, 1800000);
/* Set vbuck1 sleep voltage is 0.8V */
val = 0x10;
pmic_reg_write(p_power, 0x30, val);
}
void ldo_mode_set(int ldo_bypass)
{
u32 value;
int is_400M;
struct pmic *p = pfuze;
if (!p) {
printf("No pmic!\n");
return;
}
/* swith to ldo_bypass mode */
if (ldo_bypass) {
prep_anatop_bypass();
/* decrease VDDARM to 1.1V */
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
value &= ~0x3f;
value |= 0x20;
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
/* increase VDDSOC to 1.3V */
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
value &= ~0x3f;
value |= 0x28;
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
is_400M = set_anatop_bypass(0);
/*
* MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M
* VDDARM:0.975V@400M; VDDSOC:1.175V@400M
*/
pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
value &= ~0x3f;
if (is_400M)
value |= 0x1b;
else
value |= 0x23;
pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
/* decrease VDDSOC to 1.175V */
pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
value &= ~0x3f;
value |= 0x23;
pmic_reg_write(p, PFUZE100_SW1CVOL, value);
finish_anatop_bypass();
printf("switch to ldo_bypass mode!\n");
}
}
static int s5pc1xx_phy_control(int on)
{
struct udevice *dev;
static int status;
int reg, ret;
ret = pmic_get("max8998-pmic", &dev);
if (ret)
return ret;
if (on && !status) {
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
reg |= MAX8998_LDO3;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
reg |= MAX8998_LDO8;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
status = 1;
} else if (!on && status) {
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
reg &= ~MAX8998_LDO3;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
reg &= ~MAX8998_LDO8;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
if (ret) {
puts("MAX8998 LDO setting error!\n");
return -EINVAL;
}
status = 0;
}
udelay(10000);
return 0;
}
static int adc_power_control(int on)
{
struct udevice *dev;
int ret;
u8 reg;
ret = pmic_get("max8998-pmic", &dev);
if (ret) {
puts("Failed to get MAX8998!\n");
return ret;
}
reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
if (on)
reg |= MAX8998_LDO4;
else
reg &= ~MAX8998_LDO4;
ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
if (ret) {
puts("MAX8998 LDO setting error\n");
return -EINVAL;
}
return 0;
}
static int onkey_state(struct pmic *p_base)
{
u32 status_reg1;
pmic_reg_read(p_base, PM880_REG_STATUS, &status_reg1);
return (status_reg1 & ONKEY_STATUS)?1:0;
}
static int power_key_pressed(u32 reg)
{
struct pmic *pmic;
u32 status;
u32 mask;
pmic = pmic_get(KEY_PWR_PMIC_NAME);
if (!pmic) {
printf("%s: Not found\n", KEY_PWR_PMIC_NAME);
return 0;
}
if (pmic_probe(pmic))
return 0;
if (reg == KEY_PWR_STATUS_REG)
mask = KEY_PWR_STATUS_MASK;
else
mask = KEY_PWR_INTERRUPT_MASK;
if (pmic_reg_read(pmic, reg, &status))
return 0;
return !!(status & mask);
}
static int power_chrg_get_type(struct pmic *p)
{
unsigned int val;
unsigned int charge_type, charger;
/* if probe failed, return cable none */
if (pmic_probe(p))
return CHARGER_NO;
pmic_reg_read(p, MAX77693_MUIC_STATUS2, &val);
charge_type = val & MAX77693_MUIC_CHG_MASK;
switch (charge_type) {
case MAX77693_MUIC_CHG_NO:
charger = CHARGER_NO;
break;
case MAX77693_MUIC_CHG_USB:
case MAX77693_MUIC_CHG_USB_D:
charger = CHARGER_USB;
break;
case MAX77693_MUIC_CHG_TA:
case MAX77693_MUIC_CHG_TA_1A:
charger = CHARGER_TA;
break;
case MAX77693_MUIC_CHG_TA_500:
charger = CHARGER_TA_500;
break;
default:
charger = CHARGER_UNKNOWN;
break;
}
return charger;
}
/**
* Interface to enable/disable PMIC USB type detection
*
* @pdata Pointer to the charger type detection driver data structure
* @enable Whether to enable/disable USB type detection
* return 0 on success, otherwise error code
*/
static int pmic_usb_enable_usb_det(struct pmic_usb_det_data *pdata, bool enable)
{
int ret;
u8 reg;
if (!pdata || !pdata->pdev)
return -EINVAL;
ret = pmic_reg_read(DEV3, USBPHYCTRL, ®);
if (ret) {
dev_err(pdata->pdev, "%s - fail to read DEV3 USBPHYCTRL\n",
__func__);
return ret;
}
if (enable) {
set_field(reg, USBPHYRSTB_O, 1, CLEAR);
set_field(reg, CTYP_DIS_O, 1, CLEAR);
} else {
set_field(reg, USBPHYRSTB_O, 1, SET);
set_field(reg, CTYP_DIS_O, 1, SET);
}
ret = pmic_reg_write(DEV3, USBPHYCTRL, reg);
if (ret) {
dev_err(pdata->pdev, "%s - fail to write DEV3 USBPHYCTRL\n",
__func__);
return ret;
}
return 0;
}
static int lp873x_buck_enable(struct udevice *dev, int op, bool *enable)
{
int ret;
unsigned int adr;
struct dm_regulator_uclass_platdata *uc_pdata;
uc_pdata = dev_get_uclass_platdata(dev);
adr = uc_pdata->ctrl_reg;
ret = pmic_reg_read(dev->parent, adr);
if (ret < 0)
return ret;
if (op == PMIC_OP_GET) {
ret &= LP873X_BUCK_MODE_MASK;
if (ret)
*enable = true;
else
*enable = false;
return 0;
} else if (op == PMIC_OP_SET) {
if (*enable)
ret |= LP873X_BUCK_MODE_MASK;
else
ret &= ~(LP873X_BUCK_MODE_MASK);
ret = pmic_reg_write(dev->parent, adr, ret);
if (ret)
return ret;
}
return 0;
}
int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV)
{
unsigned int val, adr;
int hex, ret;
if (buck < 5 || buck > 9) {
printf("%s: %d is an unsupported bucket number\n",
__func__, buck);
return -EINVAL;
}
adr = max77686_buck_addr[buck] + 1;
hex = max77686_buck_volt2hex(buck, uV);
if (hex < 0)
return hex;
ret = pmic_reg_read(p, adr, &val);
if (ret)
return ret;
val &= ~MAX77686_BUCK_VOLT_MASK;
ret |= pmic_reg_write(p, adr, val | hex);
return ret;
}
/**
* Set the power state for a FET
*
* @param pmic pmic structure for the tps65090
* @param fet_id Fet number to set (1..MAX_FET_NUM)
* @param set 1 to power on FET, 0 to power off
* @return -EIO if we got a comms error, -EAGAIN if the FET failed to
* change state. If all is ok, returns 0.
*/
static int tps65090_fet_set(struct pmic *pmic, int fet_id, bool set)
{
int retry;
u32 reg, value;
value = FET_CTRL_ADENFET | FET_CTRL_WAIT;
if (set)
value |= FET_CTRL_ENFET;
if (pmic_reg_write(pmic, REG_FET1_CTRL + fet_id - 1, value))
return -EIO;
/* Try reading until we get a result */
for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {
if (pmic_reg_read(pmic, REG_FET1_CTRL + fet_id - 1, ®))
return -EIO;
/* Check that the fet went into the expected state */
if (!!(reg & FET_CTRL_PGFET) == set)
return 0;
/* If we got a timeout, there is no point in waiting longer */
if (reg & FET_CTRL_TOFET)
break;
mdelay(1);
}
debug("FET %d: Power good should have set to %d but reg=%#02x\n",
fet_id, set, reg);
return -EAGAIN;
}
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
{
unsigned int val, ret, hex, adr;
if (ldo < 1 || ldo > 26) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
hex = max77686_ldo_volt2hex(ldo, uV);
if (!hex)
return -1;
ret = pmic_reg_read(p, adr, &val);
if (ret)
return ret;
val &= ~MAX77686_LDO_VOLT_MASK;
val |= hex;
ret |= pmic_reg_write(p, adr, val);
return ret;
}
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
{
unsigned int val, ret, adr, mode;
if (ldo < 1 || 26 < ldo) {
printf("%s: %d is wrong ldo number\n", __func__, ldo);
return -1;
}
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
/* mode */
switch (opmode) {
case OPMODE_OFF:
mode = MAX77686_LDO_MODE_OFF;
break;
case OPMODE_STANDBY:
switch (ldo) {
case 2:
case 6:
case 7:
case 8:
case 10:
case 11:
case 12:
case 14:
case 15:
case 16:
mode = MAX77686_LDO_MODE_STANDBY;
break;
default:
mode = 0xff;
}
break;
case OPMODE_LPM:
mode = MAX77686_LDO_MODE_LPM;
break;
case OPMODE_ON:
mode = MAX77686_LDO_MODE_ON;
break;
default:
mode = 0xff;
}
if (mode == 0xff) {
printf("%s: %d is not supported on LDO%d\n",
__func__, opmode, ldo);
return -1;
}
ret = pmic_reg_read(p, adr, &val);
if (ret)
return ret;
val &= ~MAX77686_LDO_MODE_MASK;
val |= mode;
ret |= pmic_reg_write(p, adr, val);
return ret;
}
/**
* Interface to enable/disable USBID and ACA detection
*
* @pdata Pointer to the charger type detection driver data structure
* @id_enable Whether to enable/disable USBID detection
* @aca_enable Whether to enable/disable ACA detection
* return 0 on success, otherwise error code
*/
static int pmic_usb_enable_id_aca_det(struct pmic_usb_det_data *pdata,
bool id_enable, bool aca_enable)
{
int ret;
u8 reg;
if (!pdata || !pdata->pdev)
return -EINVAL;
ret = pmic_reg_read(DEV3, USBIDCTRL, ®);
if (ret) {
dev_err(pdata->pdev, "%s - fail to read DEV3 USBIDCTRL\n",
__func__);
return ret;
}
if (id_enable) {
set_field(reg, USB_IDEN_O, 1, SET);
if (aca_enable)
set_field(reg, ACA_DETEN_O, 1, SET);
} else {
set_field(reg, USB_IDEN_O, 1, CLEAR);
set_field(reg, ACA_DETEN_O, 1, CLEAR);
}
ret = pmic_reg_write(DEV3, USBIDCTRL, reg);
if (ret) {
dev_err(pdata->pdev, "%s - fail to write DEV3 USBIDCTRL\n",
__func__);
return ret;
}
return 0;
}
static int palmas_ldo_bypass_enable(struct udevice *dev, bool enabled)
{
int type = dev_get_driver_data(dev_get_parent(dev));
struct dm_regulator_uclass_platdata *p;
unsigned int adr;
int reg;
if (type == TPS65917) {
/* bypass available only on LDO1 and LDO2 */
if (dev->driver_data > 2)
return -ENOTSUPP;
} else if (type == TPS659038) {
/* bypass available only on LDO9 */
if (dev->driver_data != 9)
return -ENOTSUPP;
}
p = dev_get_uclass_platdata(dev);
adr = p->ctrl_reg;
reg = pmic_reg_read(dev->parent, adr);
if (reg < 0)
return reg;
if (enabled)
reg |= PALMAS_LDO_BYPASS_EN;
else
reg &= ~PALMAS_LDO_BYPASS_EN;
return pmic_reg_write(dev->parent, adr, reg);
}
/* setup board specific PMIC */
int power_init_board(void)
{
struct pmic *p;
u32 id1, id2, i;
int ret;
char const *lv_mipi;
/* configure I2C multiplexer */
gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
power_pfuze100_init(I2C_PMIC);
p = pmic_get("PFUZE100");
if (!p)
return -EINVAL;
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
pmic_reg_read(p, PFUZE100_REVID, &id2);
printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
if (id2 >= 0x20)
return 0;
/* set level of MIPI if specified */
lv_mipi = getenv("lv_mipi");
if (lv_mipi)
return 0;
for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
if (!strcmp(mipi_levels[i].name, lv_mipi)) {
printf("set MIPI level %s\n",
mipi_levels[i].name);
ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
mipi_levels[i].value);
if (ret)
return ret;
}
}
return 0;
}
