void mainboard_config_superio(void)
{
const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);
const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1);
const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI);
const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV);
/* Select HWM/LED functions instead of floppy functions. */
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03);
pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24);
/* Power RAM in S3 and let the PCH handle power failure actions. */
pnp_set_logical_device(ACPI_DEV);
pnp_write_config(ACPI_DEV, 0xe4, 0x70);
/*
* Don't know what's needed here, just set the same as the vendor
* firmware.
*/
pnp_set_logical_device(IR_DEV);
pnp_write_config(IR_DEV, 0xf1, 0x5c);
nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV);
}
void sch4037_early_init(unsigned port)
{
pnp_devfn_t dev;
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_enter_conf_state(dev);
/* Auto power management */
pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
pnp_write_config(dev, 0x23, 0);
/* Enable SMSC UART 0 */
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
/* Enabled High speed, disabled MIDI support. */
pnp_write_config(dev, 0xF0, 0x02);
pnp_set_enable(dev, 1);
/* Enable keyboard */
dev = PNP_DEV(port, SCH4037_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
static void superio_init(void)
{
/* Set base address of power management unit */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 8);
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, PM_BASE);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
/* Use on-chip clock multiplier */
outb(0x03, PM_BASE);
outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
/* Wait for the clock to stabilise */
while (!(inb(PM_BASE + 1) & 0x80)) ;
/* Enable the serial ports. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 6); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
/* Set LDN 5 UART Mode */
outb(0x21, SUPERIO_CONFIG_PORT);
outb(inb(SUPERIO_CONFIG_PORT + 1) | (1 << 3), SUPERIO_CONFIG_PORT + 1);
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 3);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
}
static void f81865f_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
(dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
pnp_exit_conf_state(dev);
}
void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
static void pc87309_enable_serial(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
static void it8712f_pnp_enable(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, !!dev->enabled);
pnp_exit_ext_func_mode(dev);
}
static void lpc47m10x_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, !!dev->enabled);
pnp_exit_conf_state(dev);
}
void it8716f_enable_dev(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
/**
* If so configured, enable the specified device, otherwise
* explicitly disable it.
*
* @param dev The device to use.
*/
static void smsc_pnp_enable(device_t dev)
{
smsc_pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, !!dev->enabled);
smsc_pnp_exit_conf_state(dev);
}
static void init(struct device *dev)
{
u8 reg8;
if (!dev->enabled)
return;
switch(dev->path.pnp.device) {
case PC97307_KBCK:
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
pnp_set_enable(dev, 1); /* Enable keyboard. */
pc_keyboard_init();
break;
case PC97307_FDC:
/* Set up floppy in PS/2 mode. */
outb(0x09, SIO_CONFIG_RA);
reg8 = inb(SIO_CONFIG_RD);
reg8 = (reg8 & 0x3F) | 0x40;
outb(reg8, SIO_CONFIG_RD);
outb(reg8, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
default:
break;
}
}
/* Serial config is a fairly standard procedure. */
static void pilot_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
static void pilot_disable_serial(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
}
static void pc8374_enable_dev(pnp_devfn_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
if (iobase)
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
static void superio_init(void)
{
pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
/* Disable the watchdog. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7);
pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00);
/* Enable the serial port. */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
}
void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
/*
* Function: lpc47b272_enable_serial
* Parameters: dev - high 8 bits = Super I/O port,
* low 8 bits = logical device number (per lpc47b272.h)
* iobase - processor I/O port address to assign to this serial device
* Return Value: bool
* Description: Configure the base I/O port of the specified serial device
* and enable the serial device.
*/
static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
static inline void w83627thg_enable_serial(device_t dev, unsigned int iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
static void wilco_ec_serial_init(void)
{
pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL);
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1);
pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE));
pnp_write_config(dev, PNP_IDX_IO0, 1);
pnp_exit_conf_state(dev);
}
static void sio_init(void)
{
u8 reg;
pnp_enter_ext_func_mode(SERIAL_DEV);
/* We have 24MHz input. */
reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
/* We have GPIO for KB/MS pin. */
reg = pnp_read_config(SERIAL_DEV, 0x2a);
pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
/* We have all RESTOUT and even some reserved bits, too. */
reg = pnp_read_config(SERIAL_DEV, 0x2c);
pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
pnp_exit_ext_func_mode(SERIAL_DEV);
pnp_enter_ext_func_mode(ACPI_DEV);
pnp_set_logical_device(ACPI_DEV);
/*
* Set the delay rising time from PWROK_LP to PWROK_ST to
* 300 - 600ms, and 0 to vice versa.
*/
reg = pnp_read_config(ACPI_DEV, 0xe6);
pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
reg = pnp_read_config(ACPI_DEV, 0xe4);
pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
pnp_exit_ext_func_mode(ACPI_DEV);
pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
pnp_exit_ext_func_mode(GPIO_DEV);
}
/*
* Set the UART clock source.
*
* Possible UART clock source speeds are:
*
* 0 = 1.8462 MHz (default)
* 1 = 2 MHz
* 2 = 24 MHz
* 3 = 14.769 MHz
*
* The faster clocks allow for BAUD rates up to 2mbits.
*
* Warning: The kernel will need to be adjusted since it assumes
* a 1.8462 MHz clock.
*/
static void set_uart_clock_source(struct device *dev, u8 uart_clock)
{
u8 value;
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xf0);
value &= ~0x03;
value |= (uart_clock & 0x03);
pnp_write_config(dev, 0xf0, value);
pnp_exit_conf_mode(dev);
}
static void superio_init(void)
{
pnp_enter_ext_func_mode_alt(SUPERIO_CONFIG_PORT);
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 4); /* COM1 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
#if 0
/* Must route GPIO to UART2 before enabling this */
pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */
pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8);
pnp_set_irq0(SUPERIO_CONFIG_PORT, 3);
pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
#endif
pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT);
}
/*
* Set the UART clock source.
*
* Possible UART clock source speeds are:
*
* 0 = 1.8462 MHz (default)
* 1 = 2 MHz
* 2 = 24 MHz
* 3 = 14.769 MHz
*
* The faster clocks allow for BAUD rates up to 2mbits.
*
* Warning: The kernel will need to be adjusted since it assumes
* a 1.8462 MHz clock.
*/
static void set_uart_clock_source(device_t dev, u8 uart_clock)
{
u8 value;
w83627uhg_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xf0);
value &= ~0x03;
value |= (uart_clock & 0x03);
pnp_write_config(dev, 0xf0, value);
w83627uhg_exit_ext_func_mode(dev);
}
static void disable_sio_watchdog(device_t dev)
{
#if 0
/* FIXME move me somewhere more appropriate */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1);
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
/* disable the sio watchdog */
outb(0, NSC_WDBASE + 0);
pnp_set_enable(dev, 0);
#endif
}
/* The PC97317 needs clocks to be set up before the serial port will operate. */
static void pc97317_enable_serial(device_t dev, u16 iobase)
{
/* Set base address of power management unit. */
pnp_set_logical_device(PM_DEV);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
pnp_set_enable(dev, 1);
/* Use on-chip clock multiplier. */
outb(0x03, PM_BASE);
outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
/* Wait for the clock to stabilise. */
while(!(inb(PM_BASE + 1) & 0x80))
;
/* Set the base address of the port. */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
static inline void kbc1100_early_init(unsigned port)
{
device_t dev;
dev = PNP_DEV (port, KBC1100_KBC);
pnp_enter_conf_state(dev);
/* Serial IRQ enabled */
outb(0x25, port);
outb(0x04, port + 1);
/* Enable SMSC UART 0 */
dev = PNP_DEV (port, SMSCSUPERIO_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
pnp_set_enable(dev, 1);
/* Enable keyboard */
dev = PNP_DEV (port, KBC1100_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
pnp_set_enable(dev, 1);
/* Enable EC Channel 0 */
dev = PNP_DEV (port, KBC1100_EC0);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
/* disable the 1s timer */
outb(0xE7, 0x64);
}
static void init(device_t dev)
{
struct superio_nsc_pc97317_config *conf;
struct resource *res0, *res1;
if (!dev->enabled) {
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC97317_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case PC97317_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case PC97317_KBCK:
/* Enable keyboard */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */
pnp_set_enable(dev, 1); /* Enable keyboard */
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
pc_keyboard_init(&conf->keyboard);
break;
#if 0
case PC97317_FDC:
{
unsigned reg;
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
}
#endif
default:
break;
}
}
static void nct5572d_init(struct device *dev)
{
uint8_t byte;
uint8_t power_status;
uint8_t mouse_detected;
if (!dev->enabled)
return;
switch (dev->path.pnp.device) {
/* TODO: Might potentially need code for HWM or FDC etc. */
case NCT5572D_KBC:
/* Enable mouse controller */
pnp_enter_conf_mode_8787(dev);
byte = pnp_read_config(dev, 0x2a);
byte &= ~(0x1 << 1);
pnp_write_config(dev, 0x2a, byte);
pnp_exit_conf_mode_aa(dev);
mouse_detected = pc_keyboard_init(PROBE_AUX_DEVICE);
if (!mouse_detected) {
printk(BIOS_INFO, "%s: Disable mouse controller.",
__func__);
pnp_enter_conf_mode_8787(dev);
byte = pnp_read_config(dev, 0x2a);
byte |= 0x1 << 1;
pnp_write_config(dev, 0x2a, byte);
pnp_exit_conf_mode_aa(dev);
}
break;
case NCT5572D_ACPI:
/* Set power state after power fail */
power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&power_status, "power_on_after_fail");
pnp_enter_conf_mode_8787(dev);
pnp_set_logical_device(dev);
byte = pnp_read_config(dev, 0xe4);
byte &= ~0x60;
if (power_status == 1)
byte |= (0x1 << 5); /* Force power on */
else if (power_status == 2)
byte |= (0x2 << 5); /* Use last power state */
pnp_write_config(dev, 0xe4, byte);
pnp_exit_conf_mode_aa(dev);
printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off");
break;
}
}
static void early_superio_config(void)
{
int timeout = 100000;
pnp_devfn_t dev = PNP_DEV(0x2e, 3);
pnp_write_config(dev, 0x29, 0x06);
while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--)
udelay(1000);
/* Enable COM1 */
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_enable(dev, 1);
}
static void init_acpi(struct device *dev)
{
u8 value;
int power_on = 1;
get_option(&power_on, "power_on_after_fail");
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xe4);
value &= ~(3 << 5);
if (power_on)
value |= (1 << 5);
pnp_write_config(dev, 0xe4, value);
pnp_exit_conf_mode(dev);
}
