int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
/* get exclusive access to the device */
mutex_lock(&locks[bus]);
/* power on the device */
poweron(bus);
/* configure bus clock, in synchronous mode its calculated from
* BAUD.reg = (f_ref / (2 * f_bus) - 1)
* with f_ref := CLOCK_CORECLOCK as defined by the board */
dev(bus)->BAUD.reg = (uint8_t)(((uint32_t)CLOCK_CORECLOCK) / (2 * clk) - 1);
/* configure device to be master and set mode and pads,
*
* NOTE: we could configure the pads already during spi_init, but for
* efficiency reason we do that here, so we can do all in one single write
* to the CTRLA register */
dev(bus)->CTRLA.reg = (SERCOM_SPI_CTRLA_MODE(0x3) | /* 0x3 -> master */
SERCOM_SPI_CTRLA_DOPO(spi_config[bus].mosi_pad) |
SERCOM_SPI_CTRLA_DIPO(spi_config[bus].miso_pad) |
(mode << SERCOM_SPI_CTRLA_CPOL_Pos));
/* also no synchronization needed here, as CTRLA is write-synchronized */
/* finally enable the device */
dev(bus)->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
while (dev(bus)->SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) {}
return SPI_OK;
}
void spi_init(spi_t bus)
{
/* make sure given bus device is valid */
assert(bus < SPI_NUMOF);
/* initialize the buses lock */
mutex_init(&locks[bus]);
/* trigger pin initialization */
spi_init_pins(bus);
/* power on the bus temporarily */
poweron(bus);
/* make the base configuration: configure as SPI master, set CS inactive
* state (for HWCS lines) and clear FIFO counters and disable FIFOs */
dev(bus)->MCR = (SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS_MASK |
SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK |
SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK |
SPI_MCR_DOZE_MASK | SPI_MCR_HALT_MASK);
/* disable all DMA and interrupt requests */
dev(bus)->RSER = 0;
/* Wait for the hardware to acknowledge the halt command */
while (dev(bus)->SR & SPI_SR_TXRXS_MASK) {}
/* and power off the bus until it is actually used */
poweroff(bus);
}
int load_driver()
{
poweron();
insmod(0, 0);
sleep(1);
return 0;
}
uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
{
uint8_t prescaler;
int scale = 1;
uint32_t f_real;
if ((unsigned int)dev >= PWM_NUMOF) {
return 0;
}
/* calculate the closest possible clock presacler */
prescaler = get_prescaler(CLOCK_CORECLOCK / (freq * res), &scale);
if (prescaler == 0xff) {
return 0;
}
f_real = (CLOCK_CORECLOCK / (scale * res));
/* configure the used pins */
for (int i = 0; i < PWM_MAX_CHANNELS; i++) {
if (pwm_config[dev].chan[i].pin != GPIO_UNDEF) {
gpio_init(pwm_config[dev].chan[i].pin, GPIO_OUT);
gpio_init_mux(pwm_config[dev].chan[i].pin, pwm_config[dev].chan[i].mux);
}
}
/* power on the device */
poweron(dev);
/* reset TCC module */
_tcc(dev)->CTRLA.reg = TCC_CTRLA_SWRST;
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) {}
/* set PWM mode */
switch (mode) {
case PWM_LEFT:
_tcc(dev)->CTRLBCLR.reg = TCC_CTRLBCLR_DIR; /* count up */
break;
case PWM_RIGHT:
_tcc(dev)->CTRLBSET.reg = TCC_CTRLBSET_DIR; /* count down */
break;
case PWM_CENTER: /* currently not supported */
default:
return 0;
}
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {}
/* configure the TCC device */
_tcc(dev)->CTRLA.reg = (TCC_CTRLA_PRESCSYNC_GCLK_Val
| TCC_CTRLA_PRESCALER(prescaler));
/* select the waveform generation mode -> normal PWM */
_tcc(dev)->WAVE.reg = (TCC_WAVE_WAVEGEN_NPWM);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) {}
/* set the selected period */
_tcc(dev)->PER.reg = (res - 1);
while (_tcc(dev)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) {}
/* start PWM operation */
_tcc(dev)->CTRLA.reg |= (TCC_CTRLA_ENABLE);
/* return the actual frequency the PWM is running at */
return f_real;
}
void PLAYBACK::restartPlaybackFromZeroGround()
{
poweron(true);
FCEUMOV_ClearCommands(); // clear POWER SWITCH command caused by poweron()
currFrameCounter = 0;
// if there's no frames in current movie, create initial frame record
if (currMovieData.getNumRecords() == 0)
currMovieData.insertEmpty(-1, 1);
}
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
/* lock the bus */
mutex_lock(&locks[bus]);
/* power on device */
poweron(bus);
/* configure SCR clock field, data-width and mode */
dev(bus)->CR0 = 0;
dev(bus)->CPSR = (spi_clk_config[clk].cpsr);
dev(bus)->CR0 = ((spi_clk_config[clk].scr << 8) | mode | SSI_CR0_DSS(8));
/* enable SSI device */
dev(bus)->CR1 = SSI_CR1_SSE;
return SPI_OK;
}
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
{
(void) cs;
/* lock and power on the bus */
mutex_lock(&locks[bus]);
poweron(bus);
/* enable the device */
dev(bus)->MCR &= ~(SPI_MCR_HALT_MASK | SPI_MCR_MDIS_MASK);
/* configure clock and mode */
dev(bus)->CTAR[0] = (mode | SPI_CTAR_FMSZ(7) | spi_clk_config[clk]);
return SPI_OK;
}
void spi_init(spi_t bus)
{
assert(bus <= SPI_NUMOF);
/* temporarily power on the device */
poweron(bus);
/* configure device to be a master and disable SSI operation mode */
dev(bus)->CR1 = 0;
/* configure system clock as SSI clock source */
dev(bus)->CC = SSI_SS_IODIV;
/* and power off the bus again */
poweroff(bus);
/* trigger SPI pin configuration */
spi_init_pins(bus);
}
void spi_init(spi_t bus)
{
/* make sure given bus is good */
assert(bus < SPI_NUMOF);
/* initialize the device lock */
mutex_init(&locks[bus]);
/* configure pins and their muxes */
spi_init_pins(bus);
/* wake up device */
poweron(bus);
/* reset all device configuration */
dev(bus)->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
while ((dev(bus)->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST) ||
(dev(bus)->SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST));
/* configure base clock: using GLK GEN 0 */
#if defined(CPU_FAM_SAMD21)
GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 |
(SERCOM0_GCLK_ID_CORE + sercom_id(dev(bus))));
while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
#elif defined(CPU_FAM_SAML21)
GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + sercom_id(dev(bus))].reg =
(GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0);
#endif
/* enable receiver and configure character size to 8-bit
* no synchronization needed, as SERCOM device is not enabled */
dev(bus)->CTRLB.reg = (SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN);
/* put device back to sleep */
poweroff(bus);
}
void test_gprs(void)
{
rt_bool_t res = RT_TRUE;
res = sysconfig(); if(!res) return;
res = poweron(); if(!res) return;
rt_thread_delay(2000);
res = gprsinit(); if(!res) return;
res = msgsend("abc"); if(!res) return;
res = msgreaddata(); if(!res) return;
res = gprsconnect(); if(!res) return;
res = gprssend("abc"); if(!res) return;
res = gprsread(); if(!res) return;
res = gprstp(); if(!res) return;
res = gprstpoff(); if(!res) return;
res = closeconnect(); if(!res) return;
poweroff();
}
void
mouse(int button, int state, int x, int y)
{
static int buttonstate;
int prevst;
int i;
SDL_Rect *r;
if(button){
if(state == 1)
buttonstate |= 1<<button-1;
else
buttonstate &= ~(1<<button-1);
}
for(i = 0; i < nelem(switches); i++){
r = &switches[i].r;
if(buttonstate == 0 ||
x < r->x || x > r->x+r->w ||
y < r->y || y > r->y+r->h){
switches[i].active = 0;
continue;
}
if(!switches[i].active){
prevst = switches[i].state;
if(buttonstate & 1)
switches[i].state = !switches[i].state;
if(buttonstate & 2)
switches[i].state = 1;
if(buttonstate & 4)
switches[i].state = 0;
switches[i].active = 1;
/* state changed */
if(prevst != switches[i].state){
/* power */
if(&switches[i] == &rest_sw[3]){
if(prevst == 0)
poweron();
}
/* rim maint */
if(&switches[i] == rim_maint_sw){
if(prevst == 0)
apr.key_rim_sbr = 1;
}
}
}
}
for(i = 0; i < nelem(keys); i++){
r = &keys[i].r;
if(buttonstate == 0 ||
x < r->x || x > r->x+r->w ||
y < r->y || y > r->y+r->h){
keys[i].state = 0;
continue;
}
prevst = keys[i].state;
if(buttonstate & 1)
keys[i].state = 1;
if(buttonstate & 4)
keys[i].state = 2;
if(prevst != keys[i].state){
switch(i){
case 0: /* start */
case 1: /* cont */
case 3: /* execute, reset */
case 4: /* deposit */
case 5: /* examine */
if(keys[i].state && apr.sw_power)
apr.extpulse |= 1;
break;
case 2: /* stop */
if(keys[i].state == 1) // inst
apr.extpulse |= 2;
break;
case 6: /* on off reader */
case 7: /* punch */
break;
}
}
}
}
void menu(void)
{
char command;
while(1)
{
command = getch();
switch(command)
{
case 'I':
case 'i':
init();
break;
case 'R':
case 'r':
reset();
break;
case 'T':
case 't':
selftest();
break;
case 'A':
case 'a':
data();
break;
case 'S':
case 's':
stream();
break;
case 'P':
case 'p':
poweron();
break;
case 'D':
case 'd':
powerdown();
break;
case 'V':
case 'v':
version();
break;
case 'M':
case 'm':
asim_command();
break;
case 'X':
case 'x':
xteds();
break;
case 'O':
case 'o':
timeattone();
break;
case 'C':
case 'c':
cancel();
break;
case 'Q':
case 'q':
endwin();
_exit(0);
case 'W':
case 'w':
rawmodetoggle();
break;
default:
wprintw(w_out,"Bad Command\n");
}
}
}
static char*
reset(Ctlr *ctlr)
{
uchar rev;
char *err;
int i;
if(ctlr->power)
poweroff(ctlr);
if((err = initring(ctlr)) != nil)
return err;
if((err = poweron(ctlr)) != nil)
return err;
/* Select VMAIN power source. */
if((err = niclock(ctlr)) != nil)
return err;
prphwrite(ctlr, ApmgPs, (prphread(ctlr, ApmgPs) & ~PwrSrcMask) | PwrSrcVMain);
nicunlock(ctlr);
/* Spin until VMAIN gets selected. */
for(i = 0; i < 5000; i++){
if(csr32r(ctlr, GpioIn) & (1 << 9))
break;
delay(10);
}
/* Perform adapter initialization. */
rev = ctlr->pdev->rid;
if((rev & 0xc0) == 0x40)
csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | AlmMb);
else if(!(rev & 0x80))
csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | AlmMm);
if(ctlr->eeprom.cap == 0x80)
csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | SkuMrc);
if((ctlr->eeprom.rev & 0xf0) == 0xd0)
csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | RevD);
else
csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) & ~RevD);
if(ctlr->eeprom.type > 1)
csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | TypeB);
/* Initialize RX ring. */
if((err = niclock(ctlr)) != nil)
return err;
coherence();
csr32w(ctlr, FhRxBase, PCIWADDR(ctlr->rx.p));
csr32w(ctlr, FhRxRptrAddr, PCIWADDR(&ctlr->shared->next));
csr32w(ctlr, FhRxWptr, 0);
csr32w(ctlr, FhRxConfig,
FhRxConfigDmaEna |
FhRxConfigRdrbdEna |
FhRxConfigWrstatusEna |
FhRxConfigMaxfrag |
(Nrxlog << FhRxConfigNrdbShift) |
FhRxConfigIrqDstHost |
(1 << FhRxConfigIrqRbthShift));
USED(csr32r(ctlr, FhRssrTbl));
csr32w(ctlr, FhRxWptr, (Nrx-1) & ~7);
nicunlock(ctlr);
/* Initialize TX rings. */
if((err = niclock(ctlr)) != nil)
return err;
prphwrite(ctlr, AlmSchedMode, 2);
prphwrite(ctlr, AlmSchedArastat, 1);
prphwrite(ctlr, AlmSchedTxfact, 0x3f);
prphwrite(ctlr, AlmSchedBP1, 0x10000);
prphwrite(ctlr, AlmSchedBP2, 0x30002);
prphwrite(ctlr, AlmSchedTxf4mf, 4);
prphwrite(ctlr, AlmSchedTxf5mf, 5);
csr32w(ctlr, FhTxBase, PCIWADDR(ctlr->shared));
csr32w(ctlr, FhMsgConfig, 0xffff05a5);
for(i = 0; i < 6; i++){
csr32w(ctlr, FhCbbcCtrl+i*8, 0);
csr32w(ctlr, FhCbbcBase+i*8, 0);
csr32w(ctlr, FhTxConfig+i*32, 0x80200008);
}
nicunlock(ctlr);
USED(csr32r(ctlr, FhTxBase));
csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
csr32w(ctlr, UcodeGp1Clr, UcodeGp1CmdBlocked);
ctlr->broken = 0;
ctlr->wait.m = 0;
ctlr->wait.w = 0;
ctlr->ie = Idefmask;
csr32w(ctlr, Imr, ctlr->ie);
csr32w(ctlr, Isr, ~0);
csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill);
return nil;
}
static int
wpiinit(Ether *edev)
{
Ctlr *ctlr;
char *err;
uchar b[64];
int i, j;
Powergrp *g;
ctlr = edev->ctlr;
if((err = poweron(ctlr)) != nil)
goto Err;
if((csr32r(ctlr, EepromGp) & 0x6) == 0){
err = "bad rom signature";
goto Err;
}
/* Clear HW ownership of EEPROM. */
csr32w(ctlr, EepromGp, csr32r(ctlr, EepromGp) & ~0x180);
if((err = eepromread(ctlr, b, 1, 0x45)) != nil)
goto Err;
ctlr->eeprom.cap = b[0];
if((err = eepromread(ctlr, b, 2, 0x35)) != nil)
goto Err;
ctlr->eeprom.rev = get16(b);
if((err = eepromread(ctlr, b, 1, 0x4a)) != nil)
goto Err;
ctlr->eeprom.type = b[0];
if((err = eepromread(ctlr, b, 4, 0x60)) != nil)
goto Err;
strncpy(ctlr->eeprom.regdom, (char*)b, 4);
ctlr->eeprom.regdom[4] = '\0';
print("wpi: %X %X %X %s\n", ctlr->eeprom.cap, ctlr->eeprom.rev, ctlr->eeprom.type, ctlr->eeprom.regdom);
if((err = eepromread(ctlr, b, 6, 0x15)) != nil)
goto Err;
memmove(edev->ea, b, Eaddrlen);
for(i = 0; i < nelem(bands); i++){
if((err = eepromread(ctlr, b, 2*bands[i].nchan, bands[i].addr)) != nil)
goto Err;
for(j = 0; j < bands[i].nchan; j++){
if(!(b[j*2] & 1))
continue;
ctlr->maxpwr[bands[i].chan[j]] = b[j*2+1];
}
}
for(i = 0; i < nelem(ctlr->eeprom.pwrgrps); i++){
if((err = eepromread(ctlr, b, 64, 0x100 + i*32)) != nil)
goto Err;
g = &ctlr->eeprom.pwrgrps[i];
g->maxpwr = b[60];
g->chan = b[61];
g->temp = get16(b+62);
for(j = 0; j < 5; j++){
g->samples[j].index = b[j*4];
g->samples[j].power = b[j*4+1];
}
}
poweroff(ctlr);
return 0;
Err:
print("wpiinit: %s\n", err);
poweroff(ctlr);
return -1;
}
void pwm_poweron(pwm_t dev)
{
poweron(dev);
_tcc(dev)->CTRLA.reg |= (TCC_CTRLA_ENABLE);
}
