void bsp_start(void) { unsigned long i = 0; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; bsp_clicks_per_usec = bsp_uboot_board_info.bi_busfreq / 8000000; #endif /* HAS_UBOOT */ rtems_counter_initialize_converter(BSP_bus_frequency / 8); /* Initialize some console parameters */ for (i = 0; i < Console_Configuration_Count; ++i) { console_tbl *ct = &Console_Configuration_Ports[i]; ct->ulClock = BSP_bus_frequency; #ifdef HAS_UBOOT if (ct->deviceType == SERIAL_NS16550) { ct->pDeviceParams = (void *) bsp_uboot_board_info.bi_baudrate; } #endif } /* Disable decrementer */ PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE); /* Initialize exception handler */ ppc_exc_initialize_with_vector_base( (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size(), bsp_exc_vector_base ); /* Now it is possible to make the code execute only */ qoriq_mmu_change_perm( FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SR ); /* Initalize interrupt support */ bsp_interrupt_initialize(); /* Disable boot page translation */ qoriq.lcc.bptr &= ~BPTR_EN; }
void bsp_start(void) { null_pointer_protection(); /* * make sure BSS/SBSS is cleared */ memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables so that it can be used * latter... */ get_ppc_cpu_type(); get_ppc_cpu_revision(); /* * determine clock speed */ bsp_clock_speed = mpc55xx_get_system_clock() / MPC55XX_SYSTEM_CLOCK_DIVIDER; /* Time reference value */ bsp_clicks_per_usec = bsp_clock_speed / 1000000; /* Initialize exceptions */ ppc_exc_initialize_with_vector_base( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size(), mpc55xx_exc_vector_base ); #ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler); #endif /* Initialize interrupts */ bsp_interrupt_initialize(); #if MPC55XX_CHIP_FAMILY != 566 mpc55xx_edma_init(); #endif #ifdef MPC55XX_EMIOS_PRESCALER mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER); #endif }
/* * bsp_start * * This routine does the bulk of the system initialization. */ void bsp_start( void ) { /* * Note we can not get CPU identification dynamically. * PVR has to be set to PPC_PSIM (0xfffe) from the device * file. */ get_ppc_cpu_type(); /* * initialize the device driver parameters */ BSP_bus_frequency = (unsigned int)PSIM_INSTRUCTIONS_PER_MICROSECOND; bsp_clicks_per_usec = BSP_bus_frequency; BSP_time_base_divisor = 1; /* * Initialize default raw exception handlers. */ ppc_exc_initialize_with_vector_base( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size(), (void *) 0xfff00000 ); /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); /* * Setup BATs and enable MMU */ /* Memory */ setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW); setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0); /* PCI */ setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE); setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE); _write_MSR(_read_MSR() | MSR_DR | MSR_IR); __asm__ volatile("sync; isync"); }
void bsp_start_on_secondary_processor(void) { uint32_t cpu_index_self = _SMP_Get_current_processor(); const Per_CPU_Control *cpu_self = _Per_CPU_Get_by_index(cpu_index_self); ppc_exc_initialize_with_vector_base( (uintptr_t) cpu_self->interrupt_stack_low, rtems_configuration_get_interrupt_stack_size(), bsp_exc_vector_base ); /* Now it is possible to make the code execute only */ qoriq_mmu_change_perm( FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SR ); bsp_interrupt_facility_initialize(); start_thread_if_necessary(cpu_index_self); _SMP_Start_multitasking_on_secondary_processor(); }
void bsp_start(void) { unsigned long i = 0; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ get_ppc_cpu_type(); get_ppc_cpu_revision(); /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq / QORIQ_BUS_CLOCK_DIVIDER; bsp_clicks_per_usec = BSP_bus_frequency / 8000000; rtems_counter_initialize_converter( #ifdef __PPC_CPU_E6500__ bsp_uboot_board_info.bi_intfreq #else BSP_bus_frequency / 8 #endif ); #endif /* HAS_UBOOT */ /* Initialize some console parameters */ for (i = 0; i < console_device_count; ++i) { const console_device *dev = &console_device_table[i]; const rtems_termios_device_handler *ns16550 = #ifdef BSP_USE_UART_INTERRUPTS &ns16550_handler_interrupt; #else &ns16550_handler_polled; #endif if (dev->handler == ns16550) { ns16550_context *ctx = (ns16550_context *) dev->context; ctx->clock = BSP_bus_frequency; #ifdef HAS_UBOOT #ifdef U_BOOT_GENERIC_BOARD_INFO ctx->initial_baud = 115200; #else ctx->initial_baud = bsp_uboot_board_info.bi_baudrate; #endif #endif } } /* Initialize exception handler */ ppc_exc_initialize_with_vector_base( (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size(), bsp_exc_vector_base ); /* Now it is possible to make the code execute only */ qoriq_mmu_change_perm( FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SR ); /* Initalize interrupt support */ bsp_interrupt_initialize(); rtems_cache_coherent_add_area( bsp_section_nocacheheap_begin, (uintptr_t) bsp_section_nocacheheap_size ); /* Disable boot page translation */ #if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT) qoriq.lcc.bstar &= ~LCC_BSTAR_EN; #else qoriq.lcc.bptr &= ~BPTR_EN; #endif }