void clock_init_uart(void) { #if CONFIG_CONS_INDEX < 5 struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* uart clock source is apb2 */ writel(APB2_CLK_SRC_OSC24M| APB2_CLK_RATE_N_1| APB2_CLK_RATE_M(1), &ccm->apb2_div); /* open the clock for uart */ setbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + CONFIG_CONS_INDEX - 1)); /* deassert uart reset */ setbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_UART_SHIFT + CONFIG_CONS_INDEX - 1)); #else /* enable R_PIO and R_UART clocks, and de-assert resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); #endif }
void clock_init_uart(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; #if CONFIG_CONS_INDEX < 5 /* uart clock source is apb2 */ writel(APB2_CLK_SRC_OSC24M| APB2_CLK_RATE_N_1| APB2_CLK_RATE_M(1), &ccm->apb2_div); /* open the clock for uart */ setbits_le32(&ccm->apb2_gate, CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + CONFIG_CONS_INDEX - 1)); /* deassert uart reset */ setbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_UART_SHIFT + CONFIG_CONS_INDEX - 1)); #else /* enable R_PIO and R_UART clocks, and de-assert resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); #endif /* Dup with clock_init_safe(), drop once sun6i SPL support lands */ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); }
int rsb_init(void) { struct sunxi_rsb_reg * const rsb = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; rsb_cfg_io(); /* Enable RSB and PIO clk, and de-assert their resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); rsb_set_clk(); return rsb_set_device_mode(); }