static int ovl_layer_config(DISP_MODULE_ENUM module,
unsigned int layer,
unsigned int source,
DpColorFormat format,
unsigned long addr,
unsigned int src_x, /* ROI x offset*/
unsigned int src_y, /* ROI y offset*/
unsigned int src_pitch,
unsigned int dst_x, /* ROI x offset*/
unsigned int dst_y, /* ROI y offset*/
unsigned int dst_w, /* ROT width*/
unsigned int dst_h, /* ROI height*/
unsigned int key_en,
unsigned int key, /*color key*/
unsigned int aen, /* alpha enable*/
unsigned char alpha,
unsigned int sur_aen,
unsigned int src_alpha,
unsigned int dst_alpha,
unsigned int constant_color,
unsigned int yuv_range,
DISP_BUFFER_TYPE sec,
unsigned int is_engine_sec,
void *handle)
{
int idx = ovl_index(module);
unsigned int value = 0;
enum OVL_INPUT_FORMAT fmt = ovl_input_fmt_convert(format);
unsigned int bpp = ovl_input_fmt_bpp(fmt);
unsigned int input_swap = ovl_input_fmt_byte_swap(fmt);
unsigned int input_fmt = ovl_input_fmt_reg_value(fmt);
enum OVL_COLOR_SPACE space = ovl_input_fmt_color_space(fmt);
unsigned int offset = 0;
/*0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)*/
int color_matrix = 0x4;
unsigned int idx_offset = idx*DISP_OVL_INDEX_OFFSET;
unsigned int layer_offset = idx_offset + layer * OVL_LAYER_OFFSET;
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
unsigned int bg_h, bg_w;
#endif
switch(yuv_range)
{
case 0: color_matrix = 4; break; //BT601_full
case 1: color_matrix = 6; break; //BT601
case 2: color_matrix = 7; break; //BT709
default:
DDPERR("un-recognized yuv_range=%d! \n", yuv_range);
color_matrix = 4;
}
// DDPMSG("color matrix=%d. \n", color_matrix);
ASSERT((dst_w <= OVL_MAX_WIDTH) &&
(dst_h <= OVL_MAX_HEIGHT) &&
(layer <= 3));
if (addr == 0) {
DDPERR("source from memory, but addr is 0!\n");
ASSERT(0);
}
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("ovl%d, layer=%d, source=%s, off(x=%d, y=%d), dst(%d, %d, %d, %d),pitch=%d,"
"fmt=%s, addr=%lx, keyEn=%d, key=%d, aen=%d, alpha=%d,"
"sur_aen=%d,sur_alpha=0x%x, constant_color=0x%x, yuv_range=%d, sec=%d,ovlsec=%d\n",
idx, layer, (source==0)?"memory":"dim", src_x, src_y,dst_x, dst_y,
dst_w, dst_h, src_pitch, ovl_intput_format_name(fmt, input_swap),
addr, key_en, key, aen, alpha, sur_aen,
dst_alpha<<2 | src_alpha, constant_color, yuv_range, sec, is_engine_sec);
#endif
if(source==OVL_LAYER_SOURCE_RESERVED) //==1, means constant color
{
if(aen==0)
{
DDPERR("dim layer ahpha enable should be 1!\n");
}
if(fmt!=OVL_INPUT_FORMAT_RGB565 && fmt!=OVL_INPUT_FORMAT_RGB888)
{
//DDPERR("dim layer format should be RGB565");
fmt = OVL_INPUT_FORMAT_RGB888;
input_fmt = ovl_input_fmt_reg_value(fmt);
}
}
// DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_RDMA0_CTRL+layer_offset, 0x1);
value = (REG_FLD_VAL((L_CON_FLD_LARC), (source)) |
REG_FLD_VAL((L_CON_FLD_CFMT), (input_fmt)) |
REG_FLD_VAL((L_CON_FLD_AEN), (aen)) |
REG_FLD_VAL((L_CON_FLD_APHA), (alpha)) |
REG_FLD_VAL((L_CON_FLD_SKEN), (key_en)) |
REG_FLD_VAL((L_CON_FLD_BTSW), (input_swap)));
if (space == OVL_COLOR_SPACE_YUV)
value = value | REG_FLD_VAL((L_CON_FLD_MTX), (color_matrix));
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
value |= 0x600;
#endif
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CON+layer_offset, value);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_CLR+idx_offset+layer*4, constant_color);
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRC_SIZE+layer_offset,
dst_h<<16 | dst_w);
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
bg_h = DISP_REG_GET(idx_offset + DISP_REG_OVL_ROI_SIZE);
bg_w = bg_h & 0xFFFF;
bg_h = bg_h >> 16;
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset, ((bg_h-dst_h-dst_y)<<16)|(bg_w-dst_w-dst_x));
#else
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_OFFSET+layer_offset,
dst_y<<16 | dst_x);
#endif
#ifdef CONFIG_MTK_LCM_PHYSICAL_ROTATION_HW
offset = src_pitch*(dst_h+src_y-1)+(src_x+dst_w)*bpp-1;
#else
offset = src_x*bpp+src_y*src_pitch;
#endif
if(!is_engine_sec) {
DISP_REG_SET(handle, DISP_REG_OVL_L0_ADDR+layer_offset, addr+offset);
} else {
unsigned int size;
int m4u_port;
size = (dst_h-1)*src_pitch + dst_w*bpp;
#if defined(MTK_FB_OVL1_SUPPORT)
m4u_port = idx==0 ? M4U_PORT_DISP_OVL0 : M4U_PORT_DISP_OVL1;
#else
m4u_port = M4U_PORT_DISP_OVL0;
#endif
if(sec != DISP_SECURE_BUFFER) {
/* ovl is sec but this layer is non-sec */
/* we need to tell cmdq to help map non-sec mva to sec mva */
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_NMVA_2_MVA, addr+offset, 0, size, m4u_port);
} else {
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
offset = src_x*bpp+src_y*src_pitch;
cmdqRecWriteSecure(handle, disp_addr_convert(DISP_REG_OVL_L0_ADDR+layer_offset),
CMDQ_SAM_H_2_MVA, addr, offset, size, m4u_port);
}
}
if(key_en==1)
{
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_SRCKEY+layer_offset, key);
}
value = (((sur_aen & 0x1) << 15) |
((dst_alpha & 0x3) << 6) | ((dst_alpha & 0x3) << 4) |
((src_alpha & 0x3)<<2) | (src_alpha & 0x3));
value = (REG_FLD_VAL((L_PITCH_FLD_SUR_ALFA), (value)) |
REG_FLD_VAL((L_PITCH_FLD_LSP), (src_pitch)));
DISP_REG_SET_DIRTY(handle, DISP_REG_OVL_L0_PITCH+layer_offset, value);
if(idx==0)
{
if(primary_display_is_decouple_mode()==0)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
if(idx==1)
{
if(primary_display_is_decouple_mode()==0 && ovl_get_status()!=DDP_OVL1_STATUS_SUB)
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x6070)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x6070);
}
else
{
if(DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset)!=0x50FF)
DISP_REG_SET(handle, DISP_REG_OVL_RDMA0_MEM_GMC_SETTING+layer_offset, 0x50FF);
}
}
return 0;
}
static void disp_debug_api(unsigned int enable, char *buf)
{
if (enable == 1) {
DDPMSG("[DDP] debug=1, trigger AEE\n");
/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
} else if (enable == 2) {
ddp_mem_test();
} else if (enable == 3) {
ddp_lcd_test();
} else if (enable == 4) {
DDPAEE("test enable=%d\n", enable);
sprintf(buf, "test enable=%d\n", enable);
} else if (enable == 5) {
if (gDDPError == 0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
} else if (enable == 6) {
/*ddp_dump_analysis(DISP_MODULE_DSI0);*/
ddp_dump_reg(DISP_MODULE_DSI0);
} else if (enable == 7) {
if (dbg_log_level < 3)
dbg_log_level++;
else
dbg_log_level = 0;
pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
} else if (enable == 8) {
DDPDUMP("clock_mm setting:%u\n",
DISP_REG_GET(DISP_REG_CONFIG_C11));
if (DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000 !=
0xff000000) {
DDPDUMP
("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
DISP_REG_GET(DISP_REG_CONFIG_C11));
}
} else if (enable == 9) {
gOVLBackground = 0xFF0000FF;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 10) {
gOVLBackground = 0xFF000000;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 11) {
dispsys_irq[DISP_REG_NUM];
ddp_irq_num[DISP_REG_NUM];
unsigned int i = 0;
char *buf_temp = buf;
for (i = 0; i < DISP_REG_NUM; i++) {
DDPDUMP
("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i],
ddp_irq_num[i]);
sprintf(buf_temp,
"i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i],
ddp_irq_num[i]);
buf_temp += strlen(buf_temp);
}
} else if (enable == 12) {
if (gUltraEnable == 0)
gUltraEnable = 1;
else
gUltraEnable = 0;
pr_debug("DDP : gUltraEnable = %d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
} else if (enable == 13) {
/*int ovl_status = ovl_get_status();
config.type = DISP_SESSION_MEMORY;
config.device_id = 0;
disp_create_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
} else if (enable == 14) {
/*int ovl_status = ovl_get_status();
disp_destroy_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status()); */
} else if (enable == 15) {
/* extern smi_dumpDebugMsg(void); */
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_RDMA0);
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_OVL1);
/* dump ultra/preultra related regs */
DDPMSG("wdma_con1(2c) = 0x%x, wdma_con2(0x38) = 0x%x, rdma_gmc0(30) = 0x%x",
DISP_REG_GET(DISP_REG_WDMA_BUF_CON1), DISP_REG_GET(DISP_REG_WDMA_BUF_CON2),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0));
DDPMSG(" rdma_gmc1(38) = 0x%x, fifo_con(40) = 0x%x\n ",
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
DDPMSG(" ovl0_gmc : 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc : 0x%x, 0x%x, 0x%x, 0x%x\n ",
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING + DISP_OVL_INDEX_OFFSET));
/* dump smi regs */
/* smi_dumpDebugMsg(); */
} else if (enable == 16) {
if (gDumpMemoutCmdq == 0)
gDumpMemoutCmdq = 1;
else
gDumpMemoutCmdq = 0;
pr_debug(" DDP : gDumpMemoutCmdq = %d\n ", gDumpMemoutCmdq);
sprintf(buf, " gDumpMemoutCmdq : %d\n ", gDumpMemoutCmdq);
} else if (enable == 21) {
if (gEnableSODIControl == 0)
gEnableSODIControl = 1;
else
gEnableSODIControl = 0;
pr_debug(" DDP : gEnableSODIControl = %d\n ", gEnableSODIControl);
sprintf(buf, " gEnableSODIControl : %d\n ", gEnableSODIControl);
} else if (enable == 22) {
if (gPrefetchControl == 0)
gPrefetchControl = 1;
else
gPrefetchControl = 0;
pr_debug(" DDP : gPrefetchControl = %d\n ", gPrefetchControl);
sprintf(buf, " gPrefetchControl : %d\n ", gPrefetchControl);
} else if (enable == 23) {
if (disp_low_power_enlarge_blanking == 0)
disp_low_power_enlarge_blanking = 1;
else
disp_low_power_enlarge_blanking = 0;
pr_debug(" DDP : disp_low_power_enlarge_blanking = %d\n ",
disp_low_power_enlarge_blanking);
sprintf(buf, " disp_low_power_enlarge_blanking : %d\n ",
disp_low_power_enlarge_blanking);
} else if (enable == 24) {
if (disp_low_power_disable_ddp_clock == 0)
disp_low_power_disable_ddp_clock = 1;
else
disp_low_power_disable_ddp_clock = 0;
pr_debug(" DDP : disp_low_power_disable_ddp_clock = %d\n ",
disp_low_power_disable_ddp_clock);
sprintf(buf, " disp_low_power_disable_ddp_clock : %d\n ",
disp_low_power_disable_ddp_clock);
} else if (enable == 25) {
if (disp_low_power_disable_fence_thread == 0)
disp_low_power_disable_fence_thread = 1;
else
disp_low_power_disable_fence_thread = 0;
pr_debug(" DDP : disp_low_power_disable_fence_thread = %d\n ",
disp_low_power_disable_fence_thread);
sprintf(buf, " disp_low_power_disable_fence_thread : %d\n ",
disp_low_power_disable_fence_thread);
} else if (enable == 26) {
if (disp_low_power_remove_ovl == 0)
disp_low_power_remove_ovl = 1;
else
disp_low_power_remove_ovl = 0;
pr_debug(" DDP : disp_low_power_remove_ovl = %d\n ", disp_low_power_remove_ovl);
sprintf(buf, " disp_low_power_remove_ovl : %d\n ", disp_low_power_remove_ovl);
} else if (enable == 27) {
if (gSkipIdleDetect == 0)
gSkipIdleDetect = 1;
else
gSkipIdleDetect = 0;
pr_debug(" DDP : gSkipIdleDetect = %d\n ", gSkipIdleDetect);
sprintf(buf, " gSkipIdleDetect : %d\n ", gSkipIdleDetect);
} else if (enable == 28) {
if (gDumpClockStatus == 0)
gDumpClockStatus = 1;
else
gDumpClockStatus = 0;
pr_debug(" DDP : gDumpClockStatus = %d\n ", gDumpClockStatus);
sprintf(buf, " gDumpClockStatus : %d\n ", gDumpClockStatus);
} else if (enable == 29) {
if (gEnableUartLog == 0)
gEnableUartLog = 1;
else
gEnableUartLog = 0;
pr_debug(" DDP : gEnableUartLog = %d\n ", gEnableUartLog);
sprintf(buf, " gEnableUartLog : %d\n ", gEnableUartLog);
} else if (enable == 30) {
if (gEnableMutexRisingEdge == 0) {
gEnableMutexRisingEdge = 1;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
1);
} else {
gEnableMutexRisingEdge = 0;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING, DISP_REG_CONFIG_MUTEX0_SOF,
0);
}
pr_debug(" DDP : gEnableMutexRisingEdge = %d\n ", gEnableMutexRisingEdge);
sprintf(buf, " gEnableMutexRisingEdge : %d\n ", gEnableMutexRisingEdge);
} else if (enable == 31) {
if (gEnableReduceRegWrite == 0)
gEnableReduceRegWrite = 1;
else
gEnableReduceRegWrite = 0;
pr_debug(" DDP : gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite);
sprintf(buf, " gEnableReduceRegWrite : %d\n ", gEnableReduceRegWrite);
} else if (enable == 32) {
/* DDPAEE(" DDP : (32) gEnableReduceRegWrite = %d\n ", gEnableReduceRegWrite); */
} else if (enable == 33) {
if (gDumpConfigCMD == 0)
gDumpConfigCMD = 1;
else
gDumpConfigCMD = 0;
pr_debug(" DDP : gDumpConfigCMD = %d\n ", gDumpConfigCMD);
sprintf(buf, " gDumpConfigCMD : %d\n ", gDumpConfigCMD);
} else if (enable == 34) {
if (gESDEnableSODI == 0)
gESDEnableSODI = 1;
else
gESDEnableSODI = 0;
pr_debug(" DDP : gESDEnableSODI = %d\n ", gESDEnableSODI);
sprintf(buf, " gESDEnableSODI : %d\n ", gESDEnableSODI);
} else if (enable == 35) {
if (gEnableOVLStatusCheck == 0)
gEnableOVLStatusCheck = 1;
else
gEnableOVLStatusCheck = 0;
pr_debug(" DDP : gEnableOVLStatusCheck = %d\n ", gEnableOVLStatusCheck);
sprintf(buf, " gEnableOVLStatusCheck : %d\n ", gEnableOVLStatusCheck);
} else if (enable == 36) {
if (gResetRDMAEnable == 0)
gResetRDMAEnable = 1;
else
gResetRDMAEnable = 0;
pr_debug(" DDP : gResetRDMAEnable = %d\n ", gResetRDMAEnable);
sprintf(buf, " gResetRDMAEnable : %d\n ", gResetRDMAEnable);
} else if (enable == 37) {
unsigned int reg_value = 0;
if (gEnableIRQ == 0) {
gEnableIRQ = 1;
/* OVL0/OVL1 */
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);
/* Mutex0 */
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));
/* RDMA0 */
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x3E);
} else {
gEnableIRQ = 0;
/* OVL0/OVL1 */
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);
/* Mutex0 */
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value & (~(1 << 0)) & (~(1 << DISP_MUTEX_TOTAL)));
/* RDMA0 */
DISP_CPU_REG_SET(DISP_REG_RDMA_INT_ENABLE, 0x18);
}
pr_debug(" DDP : gEnableIRQ = %d\n ", gEnableIRQ);
sprintf(buf, " gEnableIRQ : %d\n ", gEnableIRQ);
} else if (enable == 38) {
if (gDisableSODIForTriggerLoop == 0)
gDisableSODIForTriggerLoop = 1;
else
gDisableSODIForTriggerLoop = 0;
pr_debug(" DDP : gDisableSODIForTriggerLoop = %d\n ", gDisableSODIForTriggerLoop);
sprintf(buf, " gDisableSODIForTriggerLoop : %d\n ", gDisableSODIForTriggerLoop);
} else if (enable == 39) {
cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
sprintf(buf, " enable = %d\n ", enable);
} else if (enable == 41) {
if (gResetOVLInAALTrigger == 0)
gResetOVLInAALTrigger = 1;
else
gResetOVLInAALTrigger = 0;
pr_debug(" DDP : gResetOVLInAALTrigger = %d\n ", gResetOVLInAALTrigger);
sprintf(buf, " gResetOVLInAALTrigger : %d\n ", gResetOVLInAALTrigger);
} else if (enable == 42) {
if (gDisableOVLTF == 0)
gDisableOVLTF = 1;
else
gDisableOVLTF = 0;
pr_debug(" DDP : gDisableOVLTF = %d\n ", gDisableOVLTF);
sprintf(buf, " gDisableOVLTF : %d\n ", gDisableOVLTF);
} else if (enable == 43) {
if (gDumpESDCMD == 0)
gDumpESDCMD = 1;
else
gDumpESDCMD = 0;
pr_debug(" DDP : gDumpESDCMD = %d\n ", gDumpESDCMD);
sprintf(buf, " gDumpESDCMD : %d\n ", gDumpESDCMD);
} else if (enable == 44) {
disp_dump_emi_status();
disp_dump_emi_status();
sprintf(buf, " dump emi status !\n ");
} else if (enable == 45) {
if (gEnableCMDQProfile == 0)
gEnableCMDQProfile = 1;
else
gEnableCMDQProfile = 0;
pr_debug(" DDP : gEnableCMDQProfile = %d\n ", gEnableCMDQProfile);
sprintf(buf, " gEnableCMDQProfile : %d\n ", gEnableCMDQProfile);
} else if (enable == 46) {
disp_set_pll(156);
pr_debug(" DDP : disp_set_pll = 156.\n ");
sprintf(buf, " disp_set_pll = 156.\n ");
} else if (enable == 47) {
disp_set_pll(182);
pr_debug(" DDP : disp_set_pll = 182.\n ");
sprintf(buf, " disp_set_pll = 182.\n ");
} else if (enable == 48) {
disp_set_pll(364);
pr_debug(" DDP : disp_set_pll = 364\n ");
sprintf(buf, " disp_set_pll = 364.\n ");
} else if (enable == 49) {
if (gChangeRDMAThreshold == 0)
gChangeRDMAThreshold = 1;
else
gChangeRDMAThreshold = 0;
pr_debug(" DDP : gChangeRDMAThreshold = %d\n ", gChangeRDMAThreshold);
sprintf(buf, " gChangeRDMAThreshold : %d\n ", gChangeRDMAThreshold);
} else if (enable == 50) {
if (gChangeMMClock == 0)
gChangeMMClock = 1;
else
gChangeMMClock = 0;
pr_debug(" DDP : gChangeMMClock = %d\n ", gChangeMMClock);
sprintf(buf, " gChangeMMClock : %d\n ", gChangeMMClock);
} else if (enable == 51) {
if (gEnableUnderflowAEE == 0)
gEnableUnderflowAEE = 1;
else
gEnableUnderflowAEE = 0;
pr_debug(" DDP : gEnableUnderflowAEE = %d\n ", gEnableUnderflowAEE);
sprintf(buf, " gEnableUnderflowAEE : %d\n ", gEnableUnderflowAEE);
} else if (enable == 52) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(156, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 156. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 53) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(182, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 182. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 54) {
unsigned int time;
cmdqRecHandle handle = NULL;
cmdqRecCreate(CMDQ_SCENARIO_PRIMARY_DISP, &handle);
time = disp_set_pll_by_cmdq(364, handle);
pr_debug(" DDP : disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
sprintf(buf, " disp_set_pll_by_cmdq = 364. estimate execute time = %d\n ", time);
cmdqRecDestroy(handle);
} else if (enable == 55) {
if (gIssueRequestThreshold == 0)
gIssueRequestThreshold = 1;
else
gIssueRequestThreshold = 0;
pr_debug(" DDP : gIssueRequestThreshold = %d\n ", gIssueRequestThreshold);
sprintf(buf, " gIssueRequestThreshold : %d\n ", gIssueRequestThreshold);
} else if (enable == 56) {
if (gDisableIRQWhenIdle == 0)
gDisableIRQWhenIdle = 1;
else
gDisableIRQWhenIdle = 0;
pr_debug(" DDP : gDisableIRQWhenIdle = %d\n ", gDisableIRQWhenIdle);
sprintf(buf, " gDisableIRQWhenIdle : %d\n ", gDisableIRQWhenIdle);
} else if (enable == 57) {
if (gEnableSODIWhenIdle == 0)
gEnableSODIWhenIdle = 1;
else
gEnableSODIWhenIdle = 0;
pr_debug(" DDP : gEnableSODIWhenIdle = %d\n ", gEnableSODIWhenIdle);
sprintf(buf, " gEnableSODIWhenIdle : %d\n ", gEnableSODIWhenIdle);
} else if (enable == 58) {
#ifdef DISP_ENABLE_LAYER_FRAME
if (gAddFrame == 0)
gAddFrame = 1;
else
gAddFrame = 0;
pr_debug(" DDP : gAddFrame = %d\n ", gAddFrame);
sprintf(buf, " gAddFrame : %d\n ", gAddFrame);
#else
pr_debug(" Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
sprintf(buf, " Please enable DISP_ENABLE_LAYER_FRAME in ddp_debug.h first !\n ");
#endif
} else if (enable == 40) {
sprintf(buf, " version : %d, %s\n ", 12, __TIME__);
} else if (enable==59) {
extern void ddp_reset_test(void);
ddp_reset_test();
sprintf(buf, " dp_reset_test called. \n ");
} else if (enable == 60) {
unsigned int i = 0;
int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
pr_debug("dump path status:");
for (i = 0; i < module_num; i++)
pr_debug("%s-", ddp_get_module_name(modules[i]));
pr_debug("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for (i = 0; i < module_num; i++)
ddp_dump_analysis(modules[i]);
if (primary_display_is_decouple_mode()) {
ddp_dump_analysis(DISP_MODULE_OVL0);
ddp_dump_analysis(DISP_MODULE_OVL1);
ddp_dump_analysis(DISP_MODULE_WDMA0);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
if (primary_display_is_decouple_mode()) {
ddp_dump_reg(DISP_MODULE_OVL0);
ddp_dump_reg(DISP_MODULE_OVL1);
ddp_dump_reg(DISP_MODULE_WDMA0);
}
for (i = 0; i < module_num; i++)
ddp_dump_reg(modules[i]);
}
}
//--------------------------------------------------------
// calculate disp_wdma ultra/pre-ultra setting
// to start to issue ultra from fifo having 4us data
// to stop to issue ultra until fifo having 6us data
// to start to issue pre-ultra from fifo having 6us data
// to stop to issue pre-ultra until fifo having 7us data
// the sequence is pre_ultra_low < ultra_low < pre_ultra_high < ultra_high
// 4us 6us 6us+1level 7us
//--------------------------------------------------------
void wdma_calc_ultra(unsigned int idx, unsigned int width, unsigned int height, unsigned int bpp, unsigned int frame_rate,void * handle)
{
// constant
unsigned int blank_overhead = 115; //it is 1.15, need to divide 100 later
unsigned int rdma_fifo_width = 16; //in unit of byte
//bpp is defined by disp_wdma's output format
unsigned int pre_ultra_low_time ; //in unit of 0.5 us
unsigned int ultra_low_time ; //in unit of 0.5 us
unsigned int ultra_high_time ; //in unit of 0.5 us
// working variables
unsigned int consume_levels_per_sec;
unsigned int ultra_low_level;
unsigned int pre_ultra_low_level;
unsigned int ultra_high_level;
unsigned int ultra_high_ofs;
unsigned int ultra_low_ofs;
unsigned int pre_ultra_high_ofs;
if (bpp==3) { //YV12
pre_ultra_low_time = 2; //in unit of 0.5 us
ultra_low_time = 4; //in unit of 0.5 us
ultra_high_time = 8; //in unit of 0.5 us
} else if (bpp==6) { //RGB888
pre_ultra_low_time = 2; //in unit of 0.5 us
ultra_low_time = 4; //in unit of 0.5 us
ultra_high_time = 5; //in unit of 0.5 us
}
//consume_levels_per_sec = ((long long unsigned int)width*height*frame_rate*blank_overhead*bpp)/rdma_fifo_width/100;
//change calculation order to prevent overflow of unsigned int
//bpp/2 for bpp in unit of 0.5 bytes/pixel
consume_levels_per_sec = (width*height*frame_rate*bpp/2/rdma_fifo_width/100)*blank_overhead;
// /1000000 /2 for ultra_low_time in unit of 0.5 us
ultra_low_level = (unsigned int)(ultra_low_time * consume_levels_per_sec / 1000000 / 2);
pre_ultra_low_level = (unsigned int)(pre_ultra_low_time * consume_levels_per_sec / 1000000 / 2);
ultra_high_level = (unsigned int)(ultra_high_time * consume_levels_per_sec / 1000000 / 2);
ultra_low_ofs = ultra_low_level - pre_ultra_low_level;
pre_ultra_high_ofs = 1;
ultra_high_ofs = ultra_high_level - ultra_low_level ;
ultra_low_level = 0x86;
ultra_low_ofs = 0x35;
pre_ultra_high_ofs = 1;
ultra_high_ofs = 0x1b;
//write ultra_high_ofs, pre_ultra_high_ofs, ultra_low_ofs, pre_ultra_low_ofs=pre_ultra_low_level into register DISP_WDMA_BUF_CON2
//DISP_REG_SET(handle,idx*DISP_WDMA_INDEX_OFFSET+DISP_REG_WDMA_BUF_CON2,
// ultra_low_level|(ultra_low_ofs<<8)|(pre_ultra_high_ofs<<16)|(ultra_high_ofs<<24));
// TODO: set ultra/pre-ultra by resolution and format
/*
YV12: FHD=0x19010ea2, HD=0x0b0106d6, qHD=0x060103e9
UYVY: FHD=0x22011283, HD=0x0f0108c8, qHD=0x080104e1
RGB: FHD=0x35011b44, HD=0x17010bad, qHD=0x0c0107d1
*/
if(idx==0 && primary_display_is_decouple_mode()==0)
{
DISP_REG_SET(handle,idx*DISP_WDMA_INDEX_OFFSET+DISP_REG_WDMA_BUF_CON2, 0x35011b44);
DISP_REG_SET(handle,idx*DISP_WDMA_INDEX_OFFSET+DISP_REG_WDMA_BUF_CON1, 0xD0100080);
}
else
{
DISP_REG_SET(handle,idx*DISP_WDMA_INDEX_OFFSET+DISP_REG_WDMA_BUF_CON2, 0x35011b44);
DISP_REG_SET(handle,idx*DISP_WDMA_INDEX_OFFSET+DISP_REG_WDMA_BUF_CON1, 0x50100080);
}
DDPDBG("pre_ultra_low_level = 0x%03x = %d\n", pre_ultra_low_level , pre_ultra_low_level );
DDPDBG("ultra_low_level = 0x%03x = %d\n", ultra_low_level , ultra_low_level );
DDPDBG("ultra_high_level = 0x%03x = %d\n", ultra_high_level , ultra_high_level );
DDPDBG("ultra_low_ofs = 0x%03x = %d\n", ultra_low_ofs , ultra_low_ofs );
DDPDBG("pre_ultra_high_ofs = 0x%03x = %d\n", pre_ultra_high_ofs , pre_ultra_high_ofs );
DDPDBG("ultra_high_ofs = 0x%03x = %d\n", ultra_high_ofs , ultra_high_ofs );
}
static int wdma_config_l(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void *handle)
{
WDMA_CONFIG_STRUCT* config = &pConfig->wdma_config;
int wdma_idx = wdma_index(module);
CMDQ_ENG_ENUM cmdq_engine;
if (!pConfig->wdma_dirty) {
return 0;
}
//warm reset wdma every time we use it
if(handle) {
if(/*(primary_display_is_video_mode()==0 && primary_display_is_decouple_mode()==0) ||*/
primary_display_is_decouple_mode()==1)
{
unsigned int idx_offst = wdma_idx*DISP_WDMA_INDEX_OFFSET;
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_RST, 0x01); // trigger soft reset
cmdqRecPoll(handle, disp_addr_convert(idx_offst+DISP_REG_WDMA_FLOW_CTRL_DBG), 1, 0x1);
DISP_REG_SET(handle, idx_offst+DISP_REG_WDMA_RST , 0x0); // trigger soft reset
}
}
cmdq_engine = wdma_idx==0 ? CMDQ_ENG_DISP_WDMA0 : CMDQ_ENG_DISP_WDMA1;
if(config->security == DISP_SECURE_BUFFER) {
cmdqRecSetSecure(handle, 1);
/* set engine as sec */
cmdqRecSecureEnablePortSecurity(handle, (1LL << cmdq_engine));
cmdqRecSecureEnableDAPC(handle, (1LL << cmdq_engine));
if(wdma_is_sec[wdma_idx] == 0)
DDPMSG("[SVP] switch wdma%d to sec\n", wdma_idx);
wdma_is_sec[wdma_idx] = 1;
} else {
if(wdma_is_sec[wdma_idx]) {
/* wdma is in sec stat, we need to switch it to nonsec */
cmdqRecHandle nonsec_switch_handle;
int ret;
ret = cmdqRecCreate(CMDQ_SCENARIO_DISP_PRIMARY_DISABLE_SECURE_PATH, &(nonsec_switch_handle));
if(ret)
DDPAEE("[SVP]fail to create disable handle %s ret=%d\n", __FUNCTION__, ret);
cmdqRecReset(nonsec_switch_handle);
_cmdq_insert_wait_frame_done_token_mira(nonsec_switch_handle);
cmdqRecSetSecure(nonsec_switch_handle, 1);
/*in fact, dapc/port_sec will be disabled by cmdq*/
cmdqRecSecureEnablePortSecurity(nonsec_switch_handle, (1LL << cmdq_engine));
cmdqRecSecureEnableDAPC(nonsec_switch_handle, (1LL << cmdq_engine));
cmdqRecFlushAsync(nonsec_switch_handle);
cmdqRecDestroy(nonsec_switch_handle);
DDPMSG("[SVP] switch wdma%d to nonsec\n", wdma_idx);
}
wdma_is_sec[wdma_idx] = 0;
}
if (wdma_check_input_param(config) == 0)
wdma_config(module,
config->srcWidth,
config->srcHeight,
config->clipX,
config->clipY,
config->clipWidth,
config->clipHeight,
config->outputFormat,
config->dstAddress,
config->dstPitch,
config->useSpecifiedAlpha,
config->alpha,
config->security,
handle);
return 0;
}
static void process_dbg_debug(const char *opt)
{
unsigned int enable = 0;
static disp_session_config config;
char *p;
char *buf = dbg_buf + strlen(dbg_buf);
int ret;
p = (char *)opt + 6;
ret = kstrtoul(p, 10, (long unsigned int *)&enable);
if (ret)
pr_err("DISP/%s: errno %d\n", __func__, ret);
if (enable == 1) {
DDPMSG("[DDP] debug=1, trigger AEE\n");
/* aee_kernel_exception("DDP-TEST-ASSERT", "[DDP] DDP-TEST-ASSERT"); */
} else if (enable == 2) {
ddp_mem_test();
} else if (enable == 3) {
ddp_lcd_test();
} else if (enable == 4) {
DDPAEE("test enable=%d\n", enable);
sprintf(buf, "test enable=%d\n", enable);
} else if (enable == 5) {
if (gDDPError == 0)
gDDPError = 1;
else
gDDPError = 0;
sprintf(buf, "bypass PQ: %d\n", gDDPError);
DDPMSG("bypass PQ: %d\n", gDDPError);
} else if (enable == 6) {
unsigned int i = 0;
int *modules = ddp_get_scenario_list(DDP_SCENARIO_PRIMARY_DISP);
int module_num = ddp_get_module_num(DDP_SCENARIO_PRIMARY_DISP);
pr_debug("dump path status:");
for (i = 0; i < module_num; i++)
pr_debug("%s-", ddp_get_module_name(modules[i]));
pr_debug("\n");
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_MUTEX);
for (i = 0; i < module_num; i++)
ddp_dump_analysis(modules[i]);
if (primary_display_is_decouple_mode()) {
ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
ddp_dump_analysis(DISP_MODULE_OVL1);
#endif
ddp_dump_analysis(DISP_MODULE_WDMA0);
}
ddp_dump_reg(DISP_MODULE_CONFIG);
ddp_dump_reg(DISP_MODULE_MUTEX);
if (primary_display_is_decouple_mode()) {
ddp_dump_reg(DISP_MODULE_OVL0);
ddp_dump_reg(DISP_MODULE_OVL1);
ddp_dump_reg(DISP_MODULE_WDMA0);
}
for (i = 0; i < module_num; i++)
ddp_dump_reg(modules[i]);
} else if (enable == 7) {
if (dbg_log_level < 3)
dbg_log_level++;
else
dbg_log_level = 0;
pr_debug("DDP: dbg_log_level=%d\n", dbg_log_level);
sprintf(buf, "dbg_log_level: %d\n", dbg_log_level);
} else if (enable == 8) {
DDPDUMP("clock_mm setting:%u\n", DISP_REG_GET(DISP_REG_CONFIG_C11));
if ((DISP_REG_GET(DISP_REG_CONFIG_C11) & 0xff000000) != 0xff000000)
DDPDUMP("error, MM clock bit 24~bit31 should be 1, but real value=0x%x",
DISP_REG_GET(DISP_REG_CONFIG_C11));
} else if (enable == 9) {
gOVLBackground = 0xFF0000FF;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 10) {
gOVLBackground = 0xFF000000;
pr_debug("DDP: gOVLBackground=%d\n", gOVLBackground);
sprintf(buf, "gOVLBackground: %d\n", gOVLBackground);
} else if (enable == 11) {
unsigned int i = 0;
char *buf_temp = buf;
for (i = 0; i < DISP_REG_NUM; i++) {
DDPDUMP("i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n",
i, ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
sprintf(buf_temp, "i=%d, module=%s, va=0x%lx, pa=0x%x, irq(%d,%d)\n", i,
ddp_get_reg_module_name(i), dispsys_reg[i],
ddp_reg_pa_base[i], dispsys_irq[i], ddp_irq_num[i]);
buf_temp += strlen(buf_temp);
}
} else if (enable == 12) {
if (gUltraEnable == 0)
gUltraEnable = 1;
else
gUltraEnable = 0;
pr_debug("DDP: gUltraEnable=%d\n", gUltraEnable);
sprintf(buf, "gUltraEnable: %d\n", gUltraEnable);
} else if (enable == 13) {
int ovl_status = ovl_get_status();
config.type = DISP_SESSION_MEMORY;
config.device_id = 0;
disp_create_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
ovl_get_status());
} else if (enable == 14) {
int ovl_status = ovl_get_status();
disp_destroy_session(&config);
pr_debug("old status=%d, ovl1 status=%d\n", ovl_status, ovl_get_status());
sprintf(buf, "old status=%d, ovl1 status=%d\n", ovl_status,
ovl_get_status());
} else if (enable == 15) {
/* extern smi_dumpDebugMsg(void); */
ddp_dump_analysis(DISP_MODULE_CONFIG);
ddp_dump_analysis(DISP_MODULE_RDMA0);
ddp_dump_analysis(DISP_MODULE_OVL0);
#if defined(OVL_CASCADE_SUPPORT)
ddp_dump_analysis(DISP_MODULE_OVL1);
#endif
/* dump ultra/preultra related regs */
DDPMSG("wdma_con1(2c)=0x%x, wdma_con2(0x38)=0x%x,\n",
DISP_REG_GET(DISP_REG_WDMA_BUF_CON1),
DISP_REG_GET(DISP_REG_WDMA_BUF_CON2));
DDPMSG("rdma_gmc0(30)=0x%x, rdma_gmc1(38)=0x%x, fifo_con(40)=0x%x\n",
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1),
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON));
DDPMSG("ovl0_gmc: 0x%x, 0x%x, 0x%x, 0x%x, ovl1_gmc: 0x%x, 0x%x, 0x%x, 0x%x,\n",
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING),
DISP_REG_GET(DISP_REG_OVL_RDMA0_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA1_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA2_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET),
DISP_REG_GET(DISP_REG_OVL_RDMA3_MEM_GMC_SETTING +
DISP_OVL_INDEX_OFFSET));
/* dump smi regs */
/* smi_dumpDebugMsg(); */
} else if (enable == 16) {
if (gDumpMemoutCmdq == 0)
gDumpMemoutCmdq = 1;
else
gDumpMemoutCmdq = 0;
pr_debug("DDP: gDumpMemoutCmdq=%d\n", gDumpMemoutCmdq);
sprintf(buf, "gDumpMemoutCmdq: %d\n", gDumpMemoutCmdq);
} else if (enable == 21) {
if (gEnableSODIControl == 0)
gEnableSODIControl = 1;
else
gEnableSODIControl = 0;
pr_debug("DDP: gEnableSODIControl=%d\n", gEnableSODIControl);
sprintf(buf, "gEnableSODIControl: %d\n", gEnableSODIControl);
} else if (enable == 22) {
if (gPrefetchControl == 0)
gPrefetchControl = 1;
else
gPrefetchControl = 0;
pr_debug("DDP: gPrefetchControl=%d\n", gPrefetchControl);
sprintf(buf, "gPrefetchControl: %d\n", gPrefetchControl);
} else if (enable == 23) {
if (disp_low_power_enlarge_blanking == 0)
disp_low_power_enlarge_blanking = 1;
else
disp_low_power_enlarge_blanking = 0;
pr_debug("DDP: disp_low_power_enlarge_blanking=%d\n",
disp_low_power_enlarge_blanking);
sprintf(buf, "disp_low_power_enlarge_blanking: %d\n",
disp_low_power_enlarge_blanking);
} else if (enable == 24) {
if (disp_low_power_disable_ddp_clock == 0)
disp_low_power_disable_ddp_clock = 1;
else
disp_low_power_disable_ddp_clock = 0;
pr_debug("DDP: disp_low_power_disable_ddp_clock=%d\n",
disp_low_power_disable_ddp_clock);
sprintf(buf, "disp_low_power_disable_ddp_clock: %d\n",
disp_low_power_disable_ddp_clock);
} else if (enable == 25) {
if (disp_low_power_disable_fence_thread == 0)
disp_low_power_disable_fence_thread = 1;
else
disp_low_power_disable_fence_thread = 0;
pr_debug("DDP: disp_low_power_disable_fence_thread=%d\n",
disp_low_power_disable_fence_thread);
sprintf(buf, "disp_low_power_disable_fence_thread: %d\n",
disp_low_power_disable_fence_thread);
} else if (enable == 26) {
if (disp_low_power_remove_ovl == 0)
disp_low_power_remove_ovl = 1;
else
disp_low_power_remove_ovl = 0;
pr_debug("DDP: disp_low_power_remove_ovl=%d\n", disp_low_power_remove_ovl);
sprintf(buf, "disp_low_power_remove_ovl: %d\n", disp_low_power_remove_ovl);
} else if (enable == 27) {
if (gSkipIdleDetect == 0)
gSkipIdleDetect = 1;
else
gSkipIdleDetect = 0;
pr_debug("DDP: gSkipIdleDetect=%d\n", gSkipIdleDetect);
sprintf(buf, "gSkipIdleDetect: %d\n", gSkipIdleDetect);
} else if (enable == 28) {
if (gDumpClockStatus == 0)
gDumpClockStatus = 1;
else
gDumpClockStatus = 0;
pr_debug("DDP: gDumpClockStatus=%d\n", gDumpClockStatus);
sprintf(buf, "gDumpClockStatus: %d\n", gDumpClockStatus);
} else if (enable == 29) {
if (gEnableUartLog == 0)
gEnableUartLog = 1;
else
gEnableUartLog = 0;
pr_debug("DDP: gEnableUartLog=%d\n", gEnableUartLog);
sprintf(buf, "gEnableUartLog: %d\n", gEnableUartLog);
} else if (enable == 30) {
if (gEnableMutexRisingEdge == 0) {
gEnableMutexRisingEdge = 1;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
DISP_REG_CONFIG_MUTEX0_SOF, 1);
} else {
gEnableMutexRisingEdge = 0;
DISP_REG_SET_FIELD(0, SOF_FLD_MUTEX0_SOF_TIMING,
DISP_REG_CONFIG_MUTEX0_SOF, 0);
}
pr_debug("DDP: gEnableMutexRisingEdge=%d\n", gEnableMutexRisingEdge);
sprintf(buf, "gEnableMutexRisingEdge: %d\n", gEnableMutexRisingEdge);
} else if (enable == 31) {
if (gEnableReduceRegWrite == 0)
gEnableReduceRegWrite = 1;
else
gEnableReduceRegWrite = 0;
pr_debug("DDP: gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
sprintf(buf, "gEnableReduceRegWrite: %d\n", gEnableReduceRegWrite);
} else if (enable == 32) {
DDPAEE("DDP: (32)gEnableReduceRegWrite=%d\n", gEnableReduceRegWrite);
} else if (enable == 33) {
if (gDumpConfigCMD == 0)
gDumpConfigCMD = 1;
else
gDumpConfigCMD = 0;
pr_debug("DDP: gDumpConfigCMD=%d\n", gDumpConfigCMD);
sprintf(buf, "gDumpConfigCMD: %d\n", gDumpConfigCMD);
} else if (enable == 34) {
if (gESDEnableSODI == 0)
gESDEnableSODI = 1;
else
gESDEnableSODI = 0;
pr_debug("DDP: gESDEnableSODI=%d\n", gESDEnableSODI);
sprintf(buf, "gESDEnableSODI: %d\n", gESDEnableSODI);
} else if (enable == 35) {
if (gEnableOVLStatusCheck == 0)
gEnableOVLStatusCheck = 1;
else
gEnableOVLStatusCheck = 0;
pr_debug("DDP: gEnableOVLStatusCheck=%d\n", gEnableOVLStatusCheck);
sprintf(buf, "gEnableOVLStatusCheck: %d\n", gEnableOVLStatusCheck);
} else if (enable == 36) {
if (gResetRDMAEnable == 0)
gResetRDMAEnable = 1;
else
gResetRDMAEnable = 0;
pr_debug("DDP: gResetRDMAEnable=%d\n", gResetRDMAEnable);
sprintf(buf, "gResetRDMAEnable: %d\n", gResetRDMAEnable);
} else if (enable == 37) {
unsigned int reg_value = 0;
if (gEnableIRQ == 0) {
gEnableIRQ = 1;
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e2);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e2);
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value | (1 << 0) | (1 << DISP_MUTEX_TOTAL));
} else {
gEnableIRQ = 0;
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN, 0x1e0);
DISP_CPU_REG_SET(DISP_REG_OVL_INTEN + DISP_OVL_INDEX_OFFSET, 0x1e0);
reg_value = DISP_REG_GET(DISP_REG_CONFIG_MUTEX_INTEN);
DISP_CPU_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN,
reg_value & (~(1 << 0)) &
(~(1 << DISP_MUTEX_TOTAL)));
}
pr_debug("DDP: gEnableIRQ=%d\n", gEnableIRQ);
sprintf(buf, "gEnableIRQ: %d\n", gEnableIRQ);
} else if (enable == 38) {
if (gDisableSODIForTriggerLoop == 0)
gDisableSODIForTriggerLoop = 1;
else
gDisableSODIForTriggerLoop = 0;
pr_debug("DDP: gDisableSODIForTriggerLoop=%d\n",
gDisableSODIForTriggerLoop);
sprintf(buf, "gDisableSODIForTriggerLoop: %d\n",
gDisableSODIForTriggerLoop);
} else if (enable == 39) {
cmdqCoreSetEvent(CMDQ_SYNC_TOKEN_STREAM_EOF);
cmdqCoreSetEvent(CMDQ_EVENT_DISP_RDMA0_EOF);
sprintf(buf, "enable=%d\n", enable);
} else if (enable == 41) {
if (gResetOVLInAALTrigger == 0)
gResetOVLInAALTrigger = 1;
else
gResetOVLInAALTrigger = 0;
pr_debug("DDP: gResetOVLInAALTrigger=%d\n", gResetOVLInAALTrigger);
sprintf(buf, "gResetOVLInAALTrigger: %d\n", gResetOVLInAALTrigger);
} else if (enable == 42) {
if (gDisableOVLTF == 0)
gDisableOVLTF = 1;
else
gDisableOVLTF = 0;
pr_debug("DDP: gDisableOVLTF=%d\n", gDisableOVLTF);
sprintf(buf, "gDisableOVLTF: %d\n", gDisableOVLTF);
} else if (enable == 43) {
if (gDumpESDCMD == 0)
gDumpESDCMD = 1;
else
gDumpESDCMD = 0;
pr_debug("DDP: gDumpESDCMD=%d\n", gDumpESDCMD);
sprintf(buf, "gDumpESDCMD: %d\n", gDumpESDCMD);
} else if (enable == 44) {
/* extern void disp_dump_emi_status(void); */
disp_dump_emi_status();
sprintf(buf, "dump emi status!\n");
} else if (enable == 40) {
sprintf(buf, "version: %d, %s\n", 7, __TIME__);
} else if (enable == 45) {
ddp_aee_print("DDP AEE DUMP!!\n");
} else if (enable == 46) {
ASSERT(0);
} else if (enable == 47) {
if (gEnableDSIStateCheck == 0)
gEnableDSIStateCheck = 1;
else
gEnableDSIStateCheck = 0;
pr_debug("DDP: gEnableDSIStateCheck=%d\n", gEnableDSIStateCheck);
sprintf(buf, "gEnableDSIStateCheck: %d\n", gEnableDSIStateCheck);
} else if (enable == 48) {
if (gMutexFreeRun == 0)
gMutexFreeRun = 1;
else
gMutexFreeRun = 0;
pr_debug("DDP: gMutexFreeRun=%d\n", gMutexFreeRun);
sprintf(buf, "gMutexFreeRun: %d\n", gMutexFreeRun);
}
}
