int pvr2_encoder_start(struct pvr2_hdw *hdw)
{
int status;
/* unmask some interrupts */
pvr2_write_register(hdw, 0x0048, 0xbfffffff);
/* change some GPIO data */
pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000481);
pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000000);
pvr2_encoder_vcmd(hdw,CX2341X_ENC_MUTE_VIDEO,1,
hdw->input_val == PVR2_CVAL_INPUT_RADIO ? 1 : 0);
switch (hdw->config) {
case pvr2_config_vbi:
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
0x01,0x14);
break;
case pvr2_config_mpeg:
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
0,0x13);
break;
default: /* Unhandled cases for now */
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
0,0x13);
break;
}
if (!status) {
hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
}
return status;
}
int pvr2_encoder_stop(struct pvr2_hdw *hdw)
{
int status;
/* mask all interrupts */
pvr2_write_register(hdw, 0x0048, 0xffffffff);
switch (hdw->config) {
case pvr2_config_vbi:
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
0x01,0x01,0x14);
break;
case pvr2_config_mpeg:
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
0x01,0,0x13);
break;
default: /* Unhandled cases for now */
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
0x01,0,0x13);
break;
}
/* change some GPIO data */
/* Note: Bit d7 of dir appears to control the LED. So we shut it
off here. */
pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000401);
pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000000);
if (!status) {
hdw->subsys_enabled_mask &= ~(1<<PVR2_SUBSYS_B_ENC_RUN);
}
return status;
}
int pvr2_encoder_start(struct pvr2_hdw *hdw)
{
int status;
/* unmask some interrupts */
pvr2_write_register(hdw, 0x0048, 0xbfffffff);
/* change some GPIO data */
pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000481);
pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000000);
if (hdw->config == pvr2_config_vbi) {
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
0x01,0x14);
} else if (hdw->config == pvr2_config_mpeg) {
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
0,0x13);
} else {
status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
0,0x13);
}
if (!status) {
hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
}
return status;
}
static int pvr2_debugifc_do1cmd(struct pvr2_hdw *hdw,const char *buf,
unsigned int count)
{
const char *wptr;
unsigned int wlen;
unsigned int scnt;
scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
if (!scnt) return 0;
count -= scnt; buf += scnt;
if (!wptr) return 0;
pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr);
if (debugifc_match_keyword(wptr,wlen,"reset")) {
scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
if (!scnt) return -EINVAL;
count -= scnt; buf += scnt;
if (!wptr) return -EINVAL;
if (debugifc_match_keyword(wptr,wlen,"cpu")) {
pvr2_hdw_cpureset_assert(hdw,!0);
pvr2_hdw_cpureset_assert(hdw,0);
return 0;
} else if (debugifc_match_keyword(wptr,wlen,"bus")) {
pvr2_hdw_device_reset(hdw);
} else if (debugifc_match_keyword(wptr,wlen,"soft")) {
return pvr2_hdw_cmd_powerup(hdw);
} else if (debugifc_match_keyword(wptr,wlen,"deep")) {
return pvr2_hdw_cmd_deep_reset(hdw);
} else if (debugifc_match_keyword(wptr,wlen,"firmware")) {
return pvr2_upload_firmware2(hdw);
} else if (debugifc_match_keyword(wptr,wlen,"decoder")) {
return pvr2_hdw_cmd_decoder_reset(hdw);
}
return -EINVAL;
} else if (debugifc_match_keyword(wptr,wlen,"subsys_flags")) {
unsigned long msk = 0;
unsigned long val = 0;
if (debugifc_parse_subsys_mask(buf,count,&msk,&val) != count) {
pvr2_trace(PVR2_TRACE_DEBUGIFC,
"debugifc parse error on subsys mask");
return -EINVAL;
}
pvr2_hdw_subsys_bit_chg(hdw,msk,val);
return 0;
} else if (debugifc_match_keyword(wptr,wlen,"stream_flags")) {
unsigned long msk = 0;
unsigned long val = 0;
if (debugifc_parse_subsys_mask(buf,count,&msk,&val) != count) {
pvr2_trace(PVR2_TRACE_DEBUGIFC,
"debugifc parse error on stream mask");
return -EINVAL;
}
pvr2_hdw_subsys_stream_bit_chg(hdw,msk,val);
return 0;
} else if (debugifc_match_keyword(wptr,wlen,"cpufw")) {
scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
if (!scnt) return -EINVAL;
count -= scnt; buf += scnt;
if (!wptr) return -EINVAL;
if (debugifc_match_keyword(wptr,wlen,"fetch")) {
pvr2_hdw_cpufw_set_enabled(hdw,!0);
return 0;
} else if (debugifc_match_keyword(wptr,wlen,"done")) {
pvr2_hdw_cpufw_set_enabled(hdw,0);
return 0;
} else {
return -EINVAL;
}
} else if (debugifc_match_keyword(wptr,wlen,"gpio")) {
int dir_fl = 0;
int ret;
u32 msk,val;
scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
if (!scnt) return -EINVAL;
count -= scnt; buf += scnt;
if (!wptr) return -EINVAL;
if (debugifc_match_keyword(wptr,wlen,"dir")) {
dir_fl = !0;
} else if (!debugifc_match_keyword(wptr,wlen,"out")) {
return -EINVAL;
}
scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
if (!scnt) return -EINVAL;
count -= scnt; buf += scnt;
if (!wptr) return -EINVAL;
ret = debugifc_parse_unsigned_number(wptr,wlen,&msk);
if (ret) return ret;
scnt = debugifc_isolate_word(buf,count,&wptr,&wlen);
if (wptr) {
ret = debugifc_parse_unsigned_number(wptr,wlen,&val);
if (ret) return ret;
} else {
val = msk;
msk = 0xffffffff;
}
if (dir_fl) {
ret = pvr2_hdw_gpio_chg_dir(hdw,msk,val);
} else {
ret = pvr2_hdw_gpio_chg_out(hdw,msk,val);
}
return ret;
}
pvr2_trace(PVR2_TRACE_DEBUGIFC,
"debugifc failed to recognize cmd: \"%.*s\"",wlen,wptr);
return -EINVAL;
}
