void __init pxa_init_irq(int irq_nr, set_wake_t fn) { int irq, i; BUG_ON(irq_nr > MAX_INTERNAL_IRQS); pxa_internal_irq_nr = irq_nr; for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) { _ICMR(irq) = 0; /* disable all IRQs */ _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ } /* initialize interrupt priority */ if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { for (i = 0; i < irq_nr; i++) IPR(i) = i | (1 << 31); } /* only unmasked interrupts kick us out of idle */ ICCR = 1; for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { set_irq_chip(irq, &pxa_internal_irq_chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } pxa_internal_irq_chip.set_wake = fn; pxa_init_low_gpio_irq(fn); }
void __init pxa_init_irq(int irq_nr, set_wake_t fn) { int irq, i, n; BUG_ON(irq_nr > MAX_INTERNAL_IRQS); pxa_internal_irq_nr = irq_nr; for (n = 0; n < irq_nr; n += 32) { void __iomem *base = irq_base(n >> 5); __raw_writel(0, base + ICMR); /* disable all IRQs */ __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ for (i = n; (i < (n + 32)) && (i < irq_nr); i++) { /* initialize interrupt priority */ if (cpu_has_ipr()) __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); irq = PXA_IRQ(i); irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, handle_level_irq); irq_set_chip_data(irq, base); set_irq_flags(irq, IRQF_VALID); } } /* only unmasked interrupts kick us out of idle */ __raw_writel(1, irq_base(0) + ICCR); pxa_internal_irq_chip.irq_set_wake = fn; pxa_init_low_gpio_irq(fn); }