static void xlnx_zynqmp_ipi_init(Object *obj)
{
XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj);
DeviceState *dev = DEVICE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
RegisterInfoArray *reg_array;
char *irq_name;
int i;
memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IPI,
R_XLNX_ZYNQMP_IPI_MAX * 4);
reg_array =
register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info,
ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info),
s->regs_info, s->regs,
&xlnx_zynqmp_ipi_ops,
XLNX_ZYNQMP_IPI_ERR_DEBUG,
R_XLNX_ZYNQMP_IPI_MAX * 4);
memory_region_add_subregion(&s->iomem,
0x0,
®_array->mem);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
for (i = 0; i < NUM_IPIS; i++) {
qdev_init_gpio_out_named(dev, &s->irq_trig_out[i],
index_array_names[i], 1);
irq_name = g_strdup_printf("OBS_%s", index_array_names[i]);
qdev_init_gpio_out_named(dev, &s->irq_obs_out[i],
irq_name, 1);
g_free(irq_name);
}
}
static void altera_iic_init(Object *obj)
{
AlteraIIC *pv = ALTERA_IIC(obj);
qdev_init_gpio_in(DEVICE(pv), irq_handler, 32);
qdev_init_gpio_out_named(DEVICE(obj), &pv->parent_irq, "irq", 1);
}
static void pxa2xx_mmci_instance_init(Object *obj)
{
PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
DeviceState *dev = DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
"pxa2xx-mmci", 0x00100000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
}
static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
{
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XilinxPCIEHost *s = XILINX_PCIE_HOST(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr);
/* PCI configuration space */
pcie_host_mmcfg_init(pex, s->cfg_size);
/* MMIO region */
memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
memory_region_set_enabled(&s->mmio, false);
/* dummy PCI I/O region (not visible to the CPU) */
memory_region_init(&s->io, OBJECT(s), "io", 16);
/* interrupt out */
qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
sysbus_init_mmio(sbd, &pex->mmio);
sysbus_init_mmio(sbd, &s->mmio);
pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq,
pci_swizzle_map_irq_fn, s, &s->mmio,
&s->io, 0, 4, TYPE_PCIE_BUS);
qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
qdev_init_nofail(DEVICE(&s->root));
}
static void i8042_initfn(Object *obj)
{
ISAKBDState *isa_s = I8042(obj);
KBDState *s = &isa_s->kbd;
memory_region_init_io(isa_s->io + 0, obj, &i8042_data_ops, s,
"i8042-data", 1);
memory_region_init_io(isa_s->io + 1, obj, &i8042_cmd_ops, s,
"i8042-cmd", 1);
qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, I8042_A20_LINE, 1);
}
static void tz_ppc_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
TZPPC *s = TZ_PPC(obj);
qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS);
qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS);
qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1);
qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1);
qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1);
qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
}
static void gic_proxy_init(Object *obj)
{
GICProxy *s = XILINX_GIC_PROXY(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
DeviceState *dev = DEVICE(s);
/* IRQ grouping:
* [0..31] - GICP0
* [32..63] - GICP1
* [64..95] - GICP2
* [96..127] - GICP3
* [128..159] - GICP4
*/
qdev_init_gpio_in(dev, gic_proxy_set_irq, MAX_INTS);
qdev_init_gpio_out_named(dev, &s->irq, "gicp-irq", 1);
memory_region_init_io(&s->iomem, obj, &gic_proxy_ops, s,
TYPE_XILINX_GIC_PROXY, R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
/* Request an IRQ source. The actual IRQ object may be populated later. */
void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p)
{
qdev_init_gpio_out_named(DEVICE(dev), p, SYSBUS_DEVICE_GPIO_IRQ, 1);
}
/* EBUS (Eight bit bus) bridge */
static void ebus_realize(PCIDevice *pci_dev, Error **errp)
{
EbusState *s = EBUS(pci_dev);
SysBusDevice *sbd;
DeviceState *dev;
qemu_irq *isa_irq;
DriveInfo *fd[MAX_FD];
int i;
s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
pci_address_space_io(pci_dev), errp);
if (!s->isa_bus) {
error_setg(errp, "unable to instantiate EBUS ISA bus");
return;
}
/* ISA bus */
isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
isa_bus_irqs(s->isa_bus, isa_irq);
qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
ISA_NUM_IRQS);
/* Serial ports */
i = 0;
if (s->console_serial_base) {
serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
i++;
}
serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
/* Parallel ports */
parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
/* Keyboard */
isa_create_simple(s->isa_bus, "i8042");
/* Floppy */
for (i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
if (fd[0]) {
qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
&error_abort);
}
if (fd[1]) {
qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
&error_abort);
}
qdev_prop_set_uint32(dev, "dma", -1);
qdev_init_nofail(dev);
/* Power */
dev = qdev_create(NULL, TYPE_SUN4U_POWER);
qdev_init_nofail(dev);
sbd = SYS_BUS_DEVICE(dev);
memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
sysbus_mmio_get_region(sbd, 0));
/* PCI */
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
pci_dev->config[0x05] = 0x00;
pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
pci_dev->config[0x07] = 0x03; // status = medium devsel
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
0, 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
0, 0x8000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
}
static void ss_realize(DeviceState *dev, Error **errp)
{
SlaveBootInt *s = SBI(dev);
const char *prefix = object_get_canonical_path(OBJECT(dev));
unsigned int i;
const char *port_name;
Chardev *chr;
for (i = 0; i < ARRAY_SIZE(slave_boot_regs_info); ++i) {
DepRegisterInfo *r = &s->regs_info[
slave_boot_regs_info[i].decode.addr / 4];
*r = (DepRegisterInfo) {
.data = (uint8_t *)&s->regs[
slave_boot_regs_info[i].decode.addr / 4],
.data_size = sizeof(uint32_t),
.access = &slave_boot_regs_info[i],
.debug = SBI_ERR_DEBUG,
.prefix = prefix,
.opaque = s,
};
}
port_name = g_strdup("smap_busy_b");
qdev_init_gpio_out_named(dev, &s->smap_busy, port_name, 1);
g_free((gpointer) port_name);
port_name = g_strdup("smap_in_b");
qdev_init_gpio_in_named(dev, smap_update, port_name, 2);
g_free((gpointer) port_name);
chr = qemu_chr_find("sbi");
qdev_prop_set_chr(dev, "chardev", chr);
if (!qemu_chr_fe_get_driver(&s->chr)) {
DPRINT("SBI interface not connected\n");
} else {
qemu_chr_fe_set_handlers(&s->chr, ss_sbi_can_receive, ss_sbi_receive,
NULL, NULL, s, NULL, true);
}
fifo_create8(&s->fifo, 1024 * 4);
}
static void ss_reset(DeviceState *dev)
{
SlaveBootInt *s = SBI(dev);
uint32_t i;
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
dep_register_reset(&s->regs_info[i]);
}
fifo_reset(&s->fifo);
s->busy_line = 1;
qemu_set_irq(s->smap_busy, s->busy_line);
ss_update_busy_line(s);
sbi_update_irq(s);
/* Note : cs always 0 when rp is not connected
* i.e slave always respond to master data irrespective of
* master state
*
* as rdwr is also 0, initial state of sbi is data load. Hack this bit
* to become 1, when sbi changes to write mode. So, its assumed in
* non remote-port model master should expect data when slave wishes
* to send.
*/
}
static void rpu_realize(DeviceState *dev, Error **errp)
{
RPU *s = XILINX_RPU(dev);
const char *prefix = object_get_canonical_path(OBJECT(dev));
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rpu_regs_info); ++i) {
RegisterInfo *r = &s->regs_info[rpu_regs_info[i].decode.addr/4];
*r = (RegisterInfo) {
.data = (uint8_t *)&s->regs[
rpu_regs_info[i].decode.addr/4],
.data_size = sizeof(uint32_t),
.access = &rpu_regs_info[i],
.debug = XILINX_RPU_ERR_DEBUG,
.prefix = prefix,
.opaque = s,
};
register_init(r);
qdev_pass_all_gpios(DEVICE(r), dev);
}
if (!s->atcm1_for_rpu0) {
error_set(errp, QERR_MISSING_PARAMETER, "atcm1-for-rpu0");
return;
}
if (!s->btcm1_for_rpu0) {
error_set(errp, QERR_MISSING_PARAMETER, "btcm1-for-rpu0");
return;
}
if (!s->icache_for_rpu1) {
error_set(errp, QERR_MISSING_PARAMETER, "icache-for-rpu1");
return;
}
if (!s->dcache_for_rpu1) {
error_set(errp, QERR_MISSING_PARAMETER, "dcache-for-rpu1");
return;
}
if (!s->ddr) {
error_set(errp, QERR_MISSING_PARAMETER, "ddr-mem-for-rpu");
return;
}
/* RPUs starts in lockstep mode, so the rpu1 caches are not accessible. */
memory_region_set_enabled(s->icache_for_rpu1, false);
memory_region_set_enabled(s->dcache_for_rpu1, false);
memory_region_set_enabled(s->ddr, false);
}
static void rpu_init(Object *obj)
{
RPU *s = XILINX_RPU(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &rpu_ops, s,
TYPE_XILINX_RPU, R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq_rpu_1);
sysbus_init_irq(sbd, &s->irq_rpu_0);
/* xtcm1-for-rpu0 are the aliases for the tcm in lockstep mode.
* This link allows to enable/disable those aliases when we are in
* lock-step/normal mode.
*/
object_property_add_link(obj, "atcm1-for-rpu0", TYPE_MEMORY_REGION,
(Object **)&s->atcm1_for_rpu0,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
object_property_add_link(obj, "btcm1-for-rpu0", TYPE_MEMORY_REGION,
(Object **)&s->btcm1_for_rpu0,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
object_property_add_link(obj, "rpu1-for-main-bus", TYPE_MEMORY_REGION,
(Object **)&s->atcm1_for_rpu0,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
/* This link allows to enable/disable those memory region when we are in
* lock-step/normal mode.
*/
object_property_add_link(obj, "icache-for-rpu1", TYPE_MEMORY_REGION,
(Object **)&s->icache_for_rpu1,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
object_property_add_link(obj, "dcache-for-rpu1", TYPE_MEMORY_REGION,
(Object **)&s->dcache_for_rpu1,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
/* Link to the second part of the DDR which is enabled in split mode and
* disabled in lockstep mode.
*/
object_property_add_link(obj, "ddr-mem-for-rpu", TYPE_MEMORY_REGION,
(Object **)&s->ddr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);
/* wfi_out is used to connect to PMU GPIs. */
qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 2);
/* wfi_in is used as input from CPUs as wfi request. */
qdev_init_gpio_in_named(DEVICE(obj), zynqmp_rpu_0_handle_wfi, "wfi_in_0", 1);
qdev_init_gpio_in_named(DEVICE(obj), zynqmp_rpu_1_handle_wfi, "wfi_in_1", 1);
}
