void
beinit(struct be_softc *sc)
{
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
bus_space_handle_t cr = sc->sc_cr;
struct qec_softc *qec = sc->sc_qec;
u_int32_t v;
u_int32_t qecaddr;
u_int8_t *ea;
int s;
s = splnet();
qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
bestop(sc);
ea = sc->sc_arpcom.ac_enaddr;
bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]);
bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]);
bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]);
/* Clear hash table */
bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0);
/* Re-initialize RX configuration */
v = BE_BR_RXCFG_FIFO;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
be_mcreset(sc);
bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd);
bus_space_write_4(t, br, BE_BRI_XIFCFG,
BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV);
bus_space_write_4(t, br, BE_BRI_JSIZE, 4);
/*
* Turn off counter expiration interrupts as well as
* 'gotframe' and 'sentframe'
*/
bus_space_write_4(t, br, BE_BRI_IMASK,
BE_BR_IMASK_GOTFRAME |
BE_BR_IMASK_RCNTEXP |
BE_BR_IMASK_ACNTEXP |
BE_BR_IMASK_CCNTEXP |
BE_BR_IMASK_LCNTEXP |
BE_BR_IMASK_CVCNTEXP |
BE_BR_IMASK_SENTFRAME |
BE_BR_IMASK_NCNTEXP |
BE_BR_IMASK_ECNTEXP |
BE_BR_IMASK_LCCNTEXP |
BE_BR_IMASK_FCNTEXP |
BE_BR_IMASK_DTIMEXP);
/* Channel registers: */
bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
qecaddr = sc->sc_channel * qec->sc_msize;
bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
/* Enable transmitter */
bus_space_write_4(t, br, BE_BRI_TXCFG,
BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE);
/* Enable receiver */
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
be_ifmedia_upd(ifp);
timeout_add_sec(&sc->sc_tick_ch, 1);
splx(s);
}
int
beinit(struct ifnet *ifp)
{
struct be_softc *sc = ifp->if_softc;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
bus_space_handle_t cr = sc->sc_cr;
struct qec_softc *qec = sc->sc_qec;
uint32_t v;
uint32_t qecaddr;
uint8_t *ea;
int rc, s;
s = splnet();
qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
bestop(ifp, 1);
ea = sc->sc_enaddr;
bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]);
bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]);
bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]);
/* Clear hash table */
bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0);
/* Re-initialize RX configuration */
v = BE_BR_RXCFG_FIFO;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
be_mcreset(sc);
bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd);
bus_space_write_4(t, br,
BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV);
bus_space_write_4(t, br, BE_BRI_JSIZE, 4);
/*
* Turn off counter expiration interrupts as well as
* 'gotframe' and 'sentframe'
*/
bus_space_write_4(t, br, BE_BRI_IMASK,
BE_BR_IMASK_GOTFRAME |
BE_BR_IMASK_RCNTEXP |
BE_BR_IMASK_ACNTEXP |
BE_BR_IMASK_CCNTEXP |
BE_BR_IMASK_LCNTEXP |
BE_BR_IMASK_CVCNTEXP |
BE_BR_IMASK_SENTFRAME |
BE_BR_IMASK_NCNTEXP |
BE_BR_IMASK_ECNTEXP |
BE_BR_IMASK_LCCNTEXP |
BE_BR_IMASK_FCNTEXP |
BE_BR_IMASK_DTIMEXP);
/* Channel registers: */
bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma);
bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma);
qecaddr = sc->sc_channel * qec->sc_msize;
bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
/* Set max packet length */
v = ETHER_MAX_LEN;
if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
v += ETHER_VLAN_ENCAP_LEN;
bus_space_write_4(t, br, BE_BRI_RXMAX, v);
bus_space_write_4(t, br, BE_BRI_TXMAX, v);
/* Enable transmitter */
bus_space_write_4(t, br,
BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE);
/* Enable receiver */
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
if ((rc = be_ifmedia_upd(ifp)) != 0)
goto out;
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
callout_reset(&sc->sc_tick_ch, hz, be_tick, sc);
return 0;
out:
splx(s);
return rc;
}
void
qeinit(struct qe_softc *sc)
{
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t cr = sc->sc_cr;
bus_space_handle_t mr = sc->sc_mr;
struct qec_softc *qec = sc->sc_qec;
uint32_t qecaddr;
uint8_t *ea;
int s;
#if defined(SUN4U) || defined(__GNUC__)
(void)&t;
#endif
s = splnet();
qestop(sc);
/*
* Allocate descriptor ring and buffers
*/
qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ);
/* Channel registers: */
bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma);
bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma);
bus_space_write_4(t, cr, QE_CRI_RIMASK, 0);
bus_space_write_4(t, cr, QE_CRI_TIMASK, 0);
bus_space_write_4(t, cr, QE_CRI_QMASK, 0);
bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL);
bus_space_write_4(t, cr, QE_CRI_CCNT, 0);
bus_space_write_4(t, cr, QE_CRI_PIPG, 0);
qecaddr = sc->sc_channel * qec->sc_msize;
bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr);
bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr);
bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
/* MACE registers: */
bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL);
bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT);
bus_space_write_1(t, mr, QE_MRI_RCVFC, 0);
/*
* Mask MACE's receive interrupt, since we're being notified
* by the QEC after DMA completes.
*/
bus_space_write_1(t, mr, QE_MRI_IMR,
QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM);
bus_space_write_1(t, mr, QE_MRI_BIUCC,
QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS);
bus_space_write_1(t, mr, QE_MRI_FIFOFC,
QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 |
QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU);
bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP);
/*
* Station address
*/
ea = sc->sc_enaddr;
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR);
bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6);
/* Apply media settings */
qe_ifmedia_upd(ifp);
/*
* Clear Logical address filter
*/
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
/* Clear missed packet count (register cleared on read) */
(void)bus_space_read_1(t, mr, QE_MRI_MPC);
#if 0
/* test register: */
bus_space_write_1(t, mr, QE_MRI_UTR, 0);
#endif
/* Reset multicast filter */
qe_mcreset(sc);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
}
