void _sys_soc_power_state_post_ops(enum power_states state)
{
u32_t limit;
switch (state) {
case SYS_POWER_STATE_CPU_LPS_1:
/* Expire the timer as it is disabled in SS2. */
limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
case SYS_POWER_STATE_CPU_LPS:
__builtin_arc_seti(0);
break;
case SYS_POWER_STATE_DEEP_SLEEP:
qm_ss_power_soc_lpss_disable();
/* If flag is cleared it means the system entered in
* sleep state while we were in LPS. In that case, we
* must set ARC_READY flag so x86 core can continue
* its execution.
*/
if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) {
_quark_se_ss_ready();
__builtin_arc_seti(0);
} else {
QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY;
QM_SCSS_GP->gps0 &= ~QM_GPS0_BIT_SENSOR_WAKEUP;
}
break;
case SYS_POWER_STATE_DEEP_SLEEP_1:
case SYS_POWER_STATE_DEEP_SLEEP_2:
/* Route RTC interrupt to the current core */
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->rtc_0_int_mask);
__builtin_arc_seti(0);
break;
break;
default:
break;
}
}
int main(void)
{
qm_rtc_config_t rtc_cfg;
uint32_t aonc_start;
uint32_t rtc_trigger;
/* Initialise RTC configuration. */
rtc_cfg.init_val = 0; /* Set initial value to 0. */
rtc_cfg.alarm_en = 1; /* Enable alarm. */
rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1); /* 1s alarm. */
rtc_cfg.callback = NULL;
rtc_cfg.callback_data = NULL;
rtc_cfg.prescaler = CLK_RTC_DIV_1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
/*
* The RTC clock resides in a different clock domain
* to the system clock.
* It takes 3-4 RTC ticks for a system clock write to propagate
* to the RTC domain.
* If an entry to sleep is initiated without waiting for the
* transaction to complete the SOC will not wake from sleep.
*/
aonc_start = QM_AONC[QM_AONC_0]->aonc_cnt;
while (QM_AONC[QM_AONC_0]->aonc_cnt - aonc_start < RTC_SYNC_CLK_COUNT) {
}
QM_IR_UNMASK_INT(QM_IRQ_RTC_0_INT);
QM_IRQ_REQUEST(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);
/*
* Enable LPSS by the Sensor Subsystem.
* This will clock gate sensor peripherals.
*/
qm_ss_power_soc_lpss_enable();
/*
* Signal to the x86 core that the Sensor Subsystem
* is ready to enter LPSS mode.
*/
QM_SCSS_GP->gps2 |= QM_SCSS_GP_SENSOR_READY;
rtc_trigger = switch_rtc_to_level();
/* Go to LPSS, RTC will wake the Sensor Subsystem up. */
qm_ss_power_cpu_ss2();
/* Log the interrupt event in soc_watch. */
SOC_WATCH_LOG_EVENT(SOCW_EVENT_INTERRUPT, QM_IRQ_RTC_0_INT_VECTOR);
restore_rtc_trigger(rtc_trigger);
/* Clear the SENSOR_READY flag in General Purpose Sticky Register 2. */
QM_SCSS_GP->gps2 &= ~QM_SCSS_GP_SENSOR_READY;
/*
* Disable LPSS.
* This will restore clock gating of sensor peripherals.
*/
qm_ss_power_soc_lpss_disable();
/* Core still in C2 mode. */
qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT);
clk_sys_udelay(GPIO_TOGGLE_DELAY);
qm_gpio_set_pin(QM_GPIO_0, PIN_OUT);
clk_sys_udelay(GPIO_TOGGLE_DELAY);
qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT);
/* Set another alarm 1 second from now. */
qm_rtc_set_alarm(QM_RTC_0, QM_RTC[QM_RTC_0]->rtc_ccvr +
(QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1)));
/*
* The RTC clock resides in a different clock domain
* to the system clock.
* It takes 3-4 RTC ticks for a system clock write to propagate
* to the RTC domain.
* If an entry to sleep is initiated without waiting for the
* transaction to complete the SOC will not wake from sleep.
*/
aonc_start = QM_AONC[QM_AONC_0]->aonc_cnt;
while (QM_AONC[QM_AONC_0]->aonc_cnt - aonc_start < RTC_SYNC_CLK_COUNT) {
}
/*
* Enable LPSS by the Sensor Subsystem.
* This will clock gate sensor peripherals.
*/
qm_ss_power_soc_lpss_enable();
/*
* Signal to the x86 core that the Sensor Subsystem
* is ready to enter LPSS mode.
*/
QM_SCSS_GP->gps2 |= QM_SCSS_GP_SENSOR_READY;
rtc_trigger = switch_rtc_to_level();
/* Go to LPSS, RTC will wake the Sensor Subsystem up. */
qm_ss_power_cpu_ss2();
/* Log the interrupt event in soc_watch. */
SOC_WATCH_LOG_EVENT(SOCW_EVENT_INTERRUPT, QM_IRQ_RTC_0_INT_VECTOR);
restore_rtc_trigger(rtc_trigger);
/* Clear the SENSOR_READY flag in General Purpose Sticky Register 2. */
QM_SCSS_GP->gps2 &= ~QM_SCSS_GP_SENSOR_READY;
/*
* Disable LPSS.
* This will restore clock gating of sensor peripherals.
*/
qm_ss_power_soc_lpss_disable();
/* Core still in C2LP mode. */
qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT);
clk_sys_udelay(GPIO_TOGGLE_DELAY);
qm_gpio_set_pin(QM_GPIO_0, PIN_OUT);
clk_sys_udelay(GPIO_TOGGLE_DELAY);
qm_gpio_clear_pin(QM_GPIO_0, PIN_OUT);
/* Trigger soc_watch flush. */
SOC_WATCH_TRIGGER_FLUSH();
return 0;
}
