static int qrk_cxxxx_rtc_init(struct device* dev) { const uint32_t expected_freq = SCSS_RTC_CLK_DIV_1_HZ | SCSS_CCU_RTC_CLK_DIV_EN; qrk_cxxxx_rtc_enable(dev); uint32_t curr_freq = MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, SCSS_CCU_SYS_CLK_CTL_OFFSET) & (SCSS_CCU_RTC_CLK_DIV_EN | SCSS_RTC_CLK_DIV_MASK); pm_wakelock_init(&rtc_wakelock, RTC_WAKELOCK); // disable interrupt MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CCR) &= ~QRK_RTC_INTERRUPT_ENABLE; MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_EOI); /* Reset initial value only if RTC wasn't enabled at right frequency at * beginning of init */ if (expected_freq != curr_freq) { // Set RTC divider 4096HZ for fast uptade qrk_cxxxx_rtc_clock_frequency(SCSS_RTC_CLK_DIV_4096_HZ); /* set intial RTC value 0 */ MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CLR) = 0; while (0 != MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CCVR)) { MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CLR) = 0; } } // Set RTC divider 1HZ qrk_cxxxx_rtc_clock_frequency(SCSS_RTC_CLK_DIV_1_HZ); return 0; }
static void qrk_cxxxx_rtc_one_time_setup(struct device *rtc_dev) { OS_ERR_TYPE err; const uint32_t expected_freq = SCSS_RTC_CLK_DIV_1_HZ | SCSS_CCU_RTC_CLK_DIV_EN; qrk_cxxxx_rtc_enable(rtc_dev); rtc_wakelock_timer = timer_create(qrk_cxxxx_rtc_wakelock_timer_callback, NULL, RTC_WAKELOCK_DELAY, false, false, &err); if (E_OS_OK != err) pr_error(LOG_MODULE_DRV, "rtc_wakelock_timer err"); uint32_t curr_freq = MMIO_REG_VAL_FROM_BASE(SCSS_REGISTER_BASE, SCSS_CCU_SYS_CLK_CTL_OFFSET) & (SCSS_CCU_RTC_CLK_DIV_EN | SCSS_RTC_CLK_DIV_MASK); pm_wakelock_init(&rtc_wakelock); /* disable interrupt */ MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CCR) &= ~QRK_RTC_INTERRUPT_ENABLE; MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_EOI); /* Reset initial value only if RTC wasn't enabled at right frequency at * beginning of init */ if (expected_freq != curr_freq) { /* Set RTC divider 4096HZ for fast update */ qrk_cxxxx_rtc_clock_frequency(SCSS_RTC_CLK_DIV_4096_HZ); /* set intial RTC value 0 */ MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CLR) = 0; while (0 != MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CCVR)) { MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR, QRK_RTC_CLR) = 0; } } }
static int qrk_cxxxx_rtc_resume(struct device* dev) { qrk_cxxxx_rtc_enable(dev); return 0; }