static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags)
{
struct r300_atom *atom;
r300_emit_hyperz_end(r300);
r300_emit_query_end(r300);
if (r300->screen->caps.is_r500)
r500_emit_index_bias(r300, 0);
r300->flush_counter++;
r300->rws->cs_flush(r300->cs, flags);
r300->dirty_hw = 0;
/* New kitchen sink, baby. */
foreach_atom(r300, atom) {
if (atom->state || atom->allow_null_state) {
r300_mark_atom_dirty(r300, atom);
}
}
r300->vertex_arrays_dirty = TRUE;
/* Unmark HWTCL state for SWTCL. */
if (!r300->screen->caps.has_tcl) {
r300->vs_state.dirty = FALSE;
r300->vs_constants.dirty = FALSE;
r300->clip_state.dirty = FALSE;
}
}
static void r300_resource_resolve(struct pipe_context *pipe,
const struct pipe_resolve_info *info)
{
struct r300_context *r300 = r300_context(pipe);
struct pipe_surface *srcsurf, *dstsurf, surf_tmpl;
struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
static const union pipe_color_union color;
memset(&surf_tmpl, 0, sizeof(surf_tmpl));
surf_tmpl.format = info->src.res->format;
surf_tmpl.u.tex.first_layer =
surf_tmpl.u.tex.last_layer = info->src.layer;
srcsurf = pipe->create_surface(pipe, info->src.res, &surf_tmpl);
/* XXX Offset both surfaces by x0,y1. */
surf_tmpl.format = info->dst.res->format;
surf_tmpl.u.tex.level = info->dst.level;
surf_tmpl.u.tex.first_layer =
surf_tmpl.u.tex.last_layer = info->dst.layer;
dstsurf = pipe->create_surface(pipe, info->dst.res, &surf_tmpl);
DBG(r300, DBG_DRAW, "r300: Resolving resource...\n");
/* Enable AA resolve. */
aa->dest = r300_surface(dstsurf);
aa->aaresolve_ctl =
R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE |
R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE;
r300->aa_state.size = 10;
r300_mark_atom_dirty(r300, &r300->aa_state);
/* Resolve the surface. */
/* XXX: y1 < 0 ==> Y flip */
r300->context.clear_render_target(pipe,
srcsurf, &color, 0, 0,
info->dst.x1 - info->dst.x0,
info->dst.y1 - info->dst.y0);
/* Disable AA resolve. */
aa->aaresolve_ctl = 0;
r300->aa_state.size = 4;
r300_mark_atom_dirty(r300, &r300->aa_state);
pipe_surface_reference(&srcsurf, NULL);
pipe_surface_reference(&dstsurf, NULL);
}
static void r300_simple_msaa_resolve(struct pipe_context *pipe,
struct pipe_resource *dst,
unsigned dst_level,
unsigned dst_layer,
struct pipe_resource *src,
enum pipe_format format)
{
struct r300_context *r300 = r300_context(pipe);
struct r300_surface *srcsurf, *dstsurf;
struct pipe_surface surf_tmpl;
struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state;
memset(&surf_tmpl, 0, sizeof(surf_tmpl));
surf_tmpl.format = format;
srcsurf = r300_surface(pipe->create_surface(pipe, src, &surf_tmpl));
surf_tmpl.format = format;
surf_tmpl.u.tex.level = dst_level;
surf_tmpl.u.tex.first_layer =
surf_tmpl.u.tex.last_layer = dst_layer;
dstsurf = r300_surface(pipe->create_surface(pipe, dst, &surf_tmpl));
/* COLORPITCH should contain the tiling info of the resolve buffer.
* The tiling of the AA buffer isn't programmable anyway. */
srcsurf->pitch &= ~(R300_COLOR_TILE(1) | R300_COLOR_MICROTILE(3));
srcsurf->pitch |= dstsurf->pitch & (R300_COLOR_TILE(1) | R300_COLOR_MICROTILE(3));
/* Enable AA resolve. */
aa->dest = dstsurf;
r300->aa_state.size = 8;
r300_mark_atom_dirty(r300, &r300->aa_state);
/* Resolve the surface. */
r300_blitter_begin(r300, R300_CLEAR_SURFACE);
util_blitter_custom_color(r300->blitter, &srcsurf->base, NULL);
r300_blitter_end(r300);
/* Disable AA resolve. */
aa->dest = NULL;
r300->aa_state.size = 4;
r300_mark_atom_dirty(r300, &r300->aa_state);
pipe_surface_reference((struct pipe_surface**)&srcsurf, NULL);
pipe_surface_reference((struct pipe_surface**)&dstsurf, NULL);
}
void r300_decompress_zmask(struct r300_context *r300)
{
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
if (!r300->zmask_in_use || r300->locked_zbuffer)
return;
r300->zmask_decompress = TRUE;
r300_mark_atom_dirty(r300, &r300->hyperz_state);
r300_blitter_begin(r300, R300_DECOMPRESS);
util_blitter_clear_depth_custom(r300->blitter, fb->width, fb->height, 0,
r300->dsa_decompress_zmask);
r300_blitter_end(r300);
r300->zmask_decompress = FALSE;
r300->zmask_in_use = FALSE;
r300_mark_atom_dirty(r300, &r300->hyperz_state);
}
static void r300_update_ztop(struct r300_context* r300)
{
struct r300_ztop_state* ztop_state =
(struct r300_ztop_state*)r300->ztop_state.state;
uint32_t old_ztop = ztop_state->z_buffer_top;
/* This is important enough that I felt it warranted a comment.
*
* According to the docs, these are the conditions where ZTOP must be
* disabled:
* 1) Alpha testing enabled
* 2) Texture kill instructions in fragment shader
* 3) Chroma key culling enabled
* 4) W-buffering enabled
*
* The docs claim that for the first three cases, if no ZS writes happen,
* then ZTOP can be used.
*
* (3) will never apply since we do not support chroma-keyed operations.
* (4) will need to be re-examined (and this comment updated) if/when
* Hyper-Z becomes supported.
*
* Additionally, the following conditions require disabled ZTOP:
* 5) Depth writes in fragment shader
* 6) Outstanding occlusion queries
*
* This register causes stalls all the way from SC to CB when changed,
* but it is buffered on-chip so it does not hurt to write it if it has
* not changed.
*
* ~C.
*/
/* ZS writes */
if (r300_dsa_writes_depth_stencil(r300->dsa_state.state) &&
(r300_dsa_alpha_test_enabled(r300->dsa_state.state) || /* (1) */
r300_fs(r300)->shader->info.uses_kill)) { /* (2) */
ztop_state->z_buffer_top = R300_ZTOP_DISABLE;
} else if (r300_fragment_shader_writes_depth(r300_fs(r300))) { /* (5) */
ztop_state->z_buffer_top = R300_ZTOP_DISABLE;
} else if (r300->query_current) { /* (6) */
ztop_state->z_buffer_top = R300_ZTOP_DISABLE;
} else {
ztop_state->z_buffer_top = R300_ZTOP_ENABLE;
}
if (ztop_state->z_buffer_top != old_ztop)
r300_mark_atom_dirty(r300, &r300->ztop_state);
}
void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
{
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
struct r300_resource *tex;
CS_LOCALS(r300);
tex = r300_resource(fb->zsbuf->texture);
BEGIN_CS(size);
OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
OUT_CS(0);
OUT_CS(tex->tex.zmask_dwords[fb->zsbuf->u.tex.level]);
OUT_CS(0);
END_CS;
/* Mark the current zbuffer's zmask as in use. */
r300->zmask_in_use = TRUE;
r300_mark_atom_dirty(r300, &r300->hyperz_state);
}
static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags,
struct pipe_fence_handle **fence)
{
struct r300_atom *atom;
r300_emit_hyperz_end(r300);
r300_emit_query_end(r300);
if (r300->screen->caps.is_r500)
r500_emit_index_bias(r300, 0);
/* The DDX doesn't set these regs. */
if (r300->screen->info.drm_minor >= 6) {
CS_LOCALS(r300);
OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
OUT_CS(0x66666666);
OUT_CS(0x6666666);
}
r300->flush_counter++;
r300->rws->cs_flush(r300->cs, flags, fence, 0);
r300->dirty_hw = 0;
/* New kitchen sink, baby. */
foreach_atom(r300, atom) {
if (atom->state || atom->allow_null_state) {
r300_mark_atom_dirty(r300, atom);
}
}
r300->vertex_arrays_dirty = TRUE;
/* Unmark HWTCL state for SWTCL. */
if (!r300->screen->caps.has_tcl) {
r300->vs_state.dirty = FALSE;
r300->vs_constants.dirty = FALSE;
r300->clip_state.dirty = FALSE;
}
}
void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
{
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
struct r300_resource* tex;
CS_LOCALS(r300);
tex = r300_resource(fb->zsbuf->texture);
BEGIN_CS(size);
OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
OUT_CS(0);
OUT_CS(tex->tex.hiz_dwords[fb->zsbuf->u.tex.level]);
OUT_CS(r300->hiz_clear_value);
END_CS;
/* Mark the current zbuffer's hiz ram as in use. */
r300->hiz_in_use = TRUE;
r300->hiz_func = HIZ_FUNC_NONE;
r300_mark_atom_dirty(r300, &r300->hyperz_state);
}
/* Clear currently bound buffers. */
static void r300_clear(struct pipe_context* pipe,
unsigned buffers,
const union pipe_color_union *color,
double depth,
unsigned stencil)
{
/* My notes about Zbuffer compression:
*
* 1) The zbuffer must be micro-tiled and whole microtiles must be
* written if compression is enabled. If microtiling is disabled,
* it locks up.
*
* 2) There is ZMASK RAM which contains a compressed zbuffer.
* Each dword of the Z Mask contains compression information
* for 16 4x4 pixel tiles, that is 2 bits for each tile.
* On chips with 2 Z pipes, every other dword maps to a different
* pipe. On newer chipsets, there is a new compression mode
* with 8x8 pixel tiles per 2 bits.
*
* 3) The FASTFILL bit has nothing to do with filling. It only tells hw
* it should look in the ZMASK RAM first before fetching from a real
* zbuffer.
*
* 4) If a pixel is in a cleared state, ZB_DEPTHCLEARVALUE is returned
* during zbuffer reads instead of the value that is actually stored
* in the zbuffer memory. A pixel is in a cleared state when its ZMASK
* is equal to 0. Therefore, if you clear ZMASK with zeros, you may
* leave the zbuffer memory uninitialized, but then you must enable
* compression, so that the ZMASK RAM is actually used.
*
* 5) Each 4x4 (or 8x8) tile is automatically decompressed and recompressed
* during zbuffer updates. A special decompressing operation should be
* used to fully decompress a zbuffer, which basically just stores all
* compressed tiles in ZMASK to the zbuffer memory.
*
* 6) For a 16-bit zbuffer, compression causes a hung with one or
* two samples and should not be used.
*
* 7) FORCE_COMPRESSED_STENCIL_VALUE should be enabled for stencil clears
* to avoid needless decompression.
*
* 8) Fastfill must not be used if reading of compressed Z data is disabled
* and writing of compressed Z data is enabled (RD/WR_COMP_ENABLE),
* i.e. it cannot be used to compress the zbuffer.
*
* 9) ZB_CB_CLEAR does not interact with zbuffer compression in any way.
*
* - Marek
*/
struct r300_context* r300 = r300_context(pipe);
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
struct r300_hyperz_state *hyperz =
(struct r300_hyperz_state*)r300->hyperz_state.state;
uint32_t width = fb->width;
uint32_t height = fb->height;
uint32_t hyperz_dcv = hyperz->zb_depthclearvalue;
/* Enable fast Z clear.
* The zbuffer must be in micro-tiled mode, otherwise it locks up. */
if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
boolean zmask_clear, hiz_clear;
zmask_clear = r300_fast_zclear_allowed(r300);
hiz_clear = r300_hiz_clear_allowed(r300);
/* If we need Hyper-Z. */
if (zmask_clear || hiz_clear) {
r300->num_z_clears++;
/* Try to obtain the access to Hyper-Z buffers if we don't have one. */
if (!r300->hyperz_enabled) {
r300->hyperz_enabled =
r300->rws->cs_request_feature(r300->cs,
RADEON_FID_R300_HYPERZ_ACCESS,
TRUE);
if (r300->hyperz_enabled) {
/* Need to emit HyperZ buffer regs for the first time. */
r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG);
}
}
/* Setup Hyper-Z clears. */
if (r300->hyperz_enabled) {
DBG(r300, DBG_HYPERZ, "r300: Clear memory: %s%s\n",
zmask_clear ? "ZMASK " : "", hiz_clear ? "HIZ" : "");
if (zmask_clear) {
hyperz_dcv = hyperz->zb_depthclearvalue =
r300_depth_clear_value(fb->zsbuf->format, depth, stencil);
r300_mark_atom_dirty(r300, &r300->zmask_clear);
buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
}
if (hiz_clear) {
r300->hiz_clear_value = r300_hiz_clear_value(depth);
r300_mark_atom_dirty(r300, &r300->hiz_clear);
}
}
}
}
/* Enable CBZB clear. */
if (r300_cbzb_clear_allowed(r300, buffers)) {
struct r300_surface *surf = r300_surface(fb->cbufs[0]);
hyperz->zb_depthclearvalue =
r300_depth_clear_cb_value(surf->base.format, color->f);
width = surf->cbzb_width;
height = surf->cbzb_height;
r300->cbzb_clear = TRUE;
r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG);
}
/* Clear. */
if (buffers) {
enum pipe_format cformat = fb->nr_cbufs ? fb->cbufs[0]->format : PIPE_FORMAT_NONE;
/* Clear using the blitter. */
r300_blitter_begin(r300, R300_CLEAR);
util_blitter_clear(r300->blitter,
width,
height,
fb->nr_cbufs,
buffers, cformat, color, depth, stencil);
r300_blitter_end(r300);
} else if (r300->zmask_clear.dirty || r300->hiz_clear.dirty) {
/* Just clear zmask and hiz now, this does not use the standard draw
* procedure. */
/* Calculate zmask_clear and hiz_clear atom sizes. */
unsigned dwords =
(r300->zmask_clear.dirty ? r300->zmask_clear.size : 0) +
(r300->hiz_clear.dirty ? r300->hiz_clear.size : 0) +
r300_get_num_cs_end_dwords(r300);
/* Reserve CS space. */
if (dwords > (RADEON_MAX_CMDBUF_DWORDS - r300->cs->cdw)) {
r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL);
}
/* Emit clear packets. */
if (r300->zmask_clear.dirty) {
r300_emit_zmask_clear(r300, r300->zmask_clear.size,
r300->zmask_clear.state);
r300->zmask_clear.dirty = FALSE;
}
if (r300->hiz_clear.dirty) {
r300_emit_hiz_clear(r300, r300->hiz_clear.size,
r300->hiz_clear.state);
r300->hiz_clear.dirty = FALSE;
}
} else {
assert(0);
}
/* Disable CBZB clear. */
if (r300->cbzb_clear) {
r300->cbzb_clear = FALSE;
hyperz->zb_depthclearvalue = hyperz_dcv;
r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG);
}
/* Enable fastfill and/or hiz.
*
* If we cleared zmask/hiz, it's in use now. The Hyper-Z state update
* looks if zmask/hiz is in use and programs hardware accordingly. */
if (r300->zmask_in_use || r300->hiz_in_use) {
r300_mark_atom_dirty(r300, &r300->hyperz_state);
}
}
static boolean r300_setup_atoms(struct r300_context* r300)
{
boolean is_rv350 = r300->screen->caps.is_rv350;
boolean is_r500 = r300->screen->caps.is_r500;
boolean has_tcl = r300->screen->caps.has_tcl;
boolean drm_2_6_0 = r300->screen->info.drm_minor >= 6;
/* Create the actual atom list.
*
* Some atoms never change size, others change every emit - those have
* the size of 0 here.
*
* NOTE: The framebuffer state is split into these atoms:
* - gpu_flush (unpipelined regs)
* - aa_state (unpipelined regs)
* - fb_state (unpipelined regs)
* - hyperz_state (unpipelined regs followed by pipelined ones)
* - fb_state_pipelined (pipelined regs)
* The motivation behind this is to be able to emit a strict
* subset of the regs, and to have reasonable register ordering. */
/* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
R300_INIT_ATOM(gpu_flush, 9);
R300_INIT_ATOM(aa_state, 4);
R300_INIT_ATOM(fb_state, 0);
R300_INIT_ATOM(hyperz_state, is_r500 || (is_rv350 && drm_2_6_0) ? 10 : 8);
/* ZB (unpipelined), SC. */
R300_INIT_ATOM(ztop_state, 2);
/* ZB, FG. */
R300_INIT_ATOM(dsa_state, is_r500 ? (drm_2_6_0 ? 10 : 8) : 6);
/* RB3D. */
R300_INIT_ATOM(blend_state, 8);
R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
/* SC. */
R300_INIT_ATOM(sample_mask, 2);
R300_INIT_ATOM(scissor_state, 3);
/* GB, FG, GA, SU, SC, RB3D. */
R300_INIT_ATOM(invariant_state, 14 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
/* VAP. */
R300_INIT_ATOM(viewport_state, 9);
R300_INIT_ATOM(pvs_flush, 2);
R300_INIT_ATOM(vap_invariant_state, is_r500 ? 11 : 9);
R300_INIT_ATOM(vertex_stream_state, 0);
R300_INIT_ATOM(vs_state, 0);
R300_INIT_ATOM(vs_constants, 0);
R300_INIT_ATOM(clip_state, has_tcl ? 3 + (6 * 4) : 0);
/* VAP, RS, GA, GB, SU, SC. */
R300_INIT_ATOM(rs_block_state, 0);
R300_INIT_ATOM(rs_state, 0);
/* SC, US. */
R300_INIT_ATOM(fb_state_pipelined, 8);
/* US. */
R300_INIT_ATOM(fs, 0);
R300_INIT_ATOM(fs_rc_constant_state, 0);
R300_INIT_ATOM(fs_constants, 0);
/* TX. */
R300_INIT_ATOM(texture_cache_inval, 2);
R300_INIT_ATOM(textures_state, 0);
/* Clear commands */
R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0);
R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0);
R300_INIT_ATOM(cmask_clear, 4);
/* ZB (unpipelined), SU. */
R300_INIT_ATOM(query_start, 4);
/* Replace emission functions for r500. */
if (is_r500) {
r300->fs.emit = r500_emit_fs;
r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
r300->fs_constants.emit = r500_emit_fs_constants;
}
/* Some non-CSO atoms need explicit space to store the state locally. */
R300_ALLOC_ATOM(aa_state, r300_aa_state);
R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
R300_ALLOC_ATOM(clip_state, r300_clip_state);
R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
R300_ALLOC_ATOM(textures_state, r300_textures_state);
R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
r300->sample_mask.state = malloc(4);
R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
if (!r300->screen->caps.has_tcl) {
R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
}
/* Some non-CSO atoms don't use the state pointer. */
r300->fb_state_pipelined.allow_null_state = TRUE;
r300->fs_rc_constant_state.allow_null_state = TRUE;
r300->pvs_flush.allow_null_state = TRUE;
r300->query_start.allow_null_state = TRUE;
r300->texture_cache_inval.allow_null_state = TRUE;
/* Some states must be marked as dirty here to properly set up
* hardware in the first command stream. */
r300_mark_atom_dirty(r300, &r300->invariant_state);
r300_mark_atom_dirty(r300, &r300->pvs_flush);
r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
r300_mark_atom_dirty(r300, &r300->textures_state);
return TRUE;
}
/* This functions is used to draw a rectangle for the blitter module.
*
* If we rendered a quad, the pixels on the main diagonal
* would be computed and stored twice, which makes the clear/copy codepaths
* somewhat inefficient. Instead we use a rectangular point sprite. */
void r300_blitter_draw_rectangle(struct blitter_context *blitter,
int x1, int y1, int x2, int y2,
float depth,
enum blitter_attrib_type type,
const union pipe_color_union *attrib)
{
struct r300_context *r300 = r300_context(util_blitter_get_pipe(blitter));
unsigned last_sprite_coord_enable = r300->sprite_coord_enable;
unsigned width = x2 - x1;
unsigned height = y2 - y1;
unsigned vertex_size =
type == UTIL_BLITTER_ATTRIB_COLOR || !r300->draw ? 8 : 4;
unsigned dwords = 13 + vertex_size +
(type == UTIL_BLITTER_ATTRIB_TEXCOORD ? 7 : 0);
static const union pipe_color_union zeros;
CS_LOCALS(r300);
/* XXX workaround for a lockup in MSAA resolve on SWTCL chipsets, this
* function most probably doesn't handle type=NONE correctly */
if (!r300->screen->caps.has_tcl && type == UTIL_BLITTER_ATTRIB_NONE) {
util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
return;
}
if (r300->skip_rendering)
return;
if (type == UTIL_BLITTER_ATTRIB_TEXCOORD)
r300->sprite_coord_enable = 1;
r300_update_derived_state(r300);
/* Mark some states we don't care about as non-dirty. */
r300->viewport_state.dirty = FALSE;
if (!r300_prepare_for_rendering(r300, PREP_EMIT_STATES, NULL, dwords, 0, 0, -1))
goto done;
DBG(r300, DBG_DRAW, "r300: draw_rectangle\n");
BEGIN_CS(dwords);
/* Set up GA. */
OUT_CS_REG(R300_GA_POINT_SIZE, (height * 6) | ((width * 6) << 16));
if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
/* Set up the GA to generate texcoords. */
OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
(R300_GB_TEX_STR << R300_GB_TEX0_SOURCE_SHIFT));
OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4);
OUT_CS_32F(attrib->f[0]);
OUT_CS_32F(attrib->f[3]);
OUT_CS_32F(attrib->f[2]);
OUT_CS_32F(attrib->f[1]);
}
/* Set up VAP controls. */
OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
OUT_CS_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_size);
OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2);
OUT_CS(1);
OUT_CS(0);
/* Draw. */
OUT_CS_PKT3(R300_PACKET3_3D_DRAW_IMMD_2, vertex_size);
OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED | (1 << 16) |
R300_VAP_VF_CNTL__PRIM_POINTS);
OUT_CS_32F(x1 + width * 0.5f);
OUT_CS_32F(y1 + height * 0.5f);
OUT_CS_32F(depth);
OUT_CS_32F(1);
if (vertex_size == 8) {
if (!attrib)
attrib = &zeros;
OUT_CS_TABLE(attrib->f, 4);
}
END_CS;
done:
/* Restore the state. */
r300_mark_atom_dirty(r300, &r300->rs_state);
r300_mark_atom_dirty(r300, &r300->viewport_state);
r300->sprite_coord_enable = last_sprite_coord_enable;
}
/* Clear currently bound buffers. */
static void r300_clear(struct pipe_context* pipe,
unsigned buffers,
const float* rgba,
double depth,
unsigned stencil)
{
/* My notes about fastfill:
*
* 1) Only the zbuffer is cleared.
*
* 2) The zbuffer must be micro-tiled and whole microtiles must be
* written. If microtiling is disabled, it locks up.
*
* 3) There is Z Mask RAM which contains a compressed zbuffer and
* it interacts with fastfill. We should figure out how to use it
* to get more performance.
* This is what we know about the Z Mask:
*
* Each dword of the Z Mask contains compression information
* for 16 4x4 pixel blocks, that is 2 bits for each block.
* On chips with 2 Z pipes, every other dword maps to a different
* pipe.
*
* 4) ZB_DEPTHCLEARVALUE is used to clear the zbuffer and the Z Mask must
* be equal to 0. (clear the Z Mask RAM with zeros)
*
* 5) For 16-bit zbuffer, compression causes a hung with one or
* two samples and should not be used.
*
* 6) FORCE_COMPRESSED_STENCIL_VALUE should be enabled for stencil clears
* to avoid needless decompression.
*
* 7) Fastfill must not be used if reading of compressed Z data is disabled
* and writing of compressed Z data is enabled (RD/WR_COMP_ENABLE),
* i.e. it cannot be used to compress the zbuffer.
*
* 8) ZB_CB_CLEAR does not interact with fastfill in any way.
*
* - Marek
*/
struct r300_context* r300 = r300_context(pipe);
struct pipe_framebuffer_state *fb =
(struct pipe_framebuffer_state*)r300->fb_state.state;
struct r300_hyperz_state *hyperz =
(struct r300_hyperz_state*)r300->hyperz_state.state;
struct r300_texture *zstex =
fb->zsbuf ? r300_texture(fb->zsbuf->texture) : NULL;
uint32_t width = fb->width;
uint32_t height = fb->height;
boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
uint32_t hyperz_dcv = hyperz->zb_depthclearvalue;
/* Enable fast Z clear.
* The zbuffer must be in micro-tiled mode, otherwise it locks up. */
if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && can_hyperz) {
hyperz_dcv = hyperz->zb_depthclearvalue =
r300_depth_clear_value(fb->zsbuf->format, depth, stencil);
r300_mark_fb_state_dirty(r300, R300_CHANGED_ZCLEAR_FLAG);
if (zstex->zmask_mem[fb->zsbuf->u.tex.level]) {
r300_mark_atom_dirty(r300, &r300->zmask_clear);
buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
}
if (zstex->hiz_mem[fb->zsbuf->u.tex.level])
r300_mark_atom_dirty(r300, &r300->hiz_clear);
}
/* Enable CBZB clear. */
if (r300_cbzb_clear_allowed(r300, buffers)) {
struct r300_surface *surf = r300_surface(fb->cbufs[0]);
hyperz->zb_depthclearvalue =
r300_depth_clear_cb_value(surf->base.format, rgba);
width = surf->cbzb_width;
height = surf->cbzb_height;
r300->cbzb_clear = TRUE;
r300_mark_fb_state_dirty(r300, R300_CHANGED_CBZB_FLAG);
}
/* Clear. */
if (buffers) {
/* Clear using the blitter. */
r300_blitter_begin(r300, R300_CLEAR);
util_blitter_clear(r300->blitter,
width,
height,
fb->nr_cbufs,
buffers, rgba, depth, stencil);
r300_blitter_end(r300);
} else if (r300->zmask_clear.dirty) {
/* Just clear zmask and hiz now, this does not use a standard draw
* procedure. */
unsigned dwords;
/* Calculate zmask_clear and hiz_clear atom sizes. */
r300_update_hyperz_state(r300);
dwords = r300->zmask_clear.size +
(r300->hiz_clear.dirty ? r300->hiz_clear.size : 0) +
r300_get_num_cs_end_dwords(r300);
/* Reserve CS space. */
if (dwords > (R300_MAX_CMDBUF_DWORDS - r300->cs->cdw)) {
r300->context.flush(&r300->context, 0, NULL);
}
/* Emit clear packets. */
r300_emit_zmask_clear(r300, r300->zmask_clear.size,
r300->zmask_clear.state);
r300->zmask_clear.dirty = FALSE;
if (r300->hiz_clear.dirty) {
r300_emit_hiz_clear(r300, r300->hiz_clear.size,
r300->hiz_clear.state);
r300->hiz_clear.dirty = FALSE;
}
} else {
assert(0);
}
/* Disable CBZB clear. */
if (r300->cbzb_clear) {
r300->cbzb_clear = FALSE;
hyperz->zb_depthclearvalue = hyperz_dcv;
r300_mark_fb_state_dirty(r300, R300_CHANGED_CBZB_FLAG);
}
/* Enable fastfill and/or hiz.
*
* If we cleared zmask/hiz, it's in use now. The Hyper-Z state update
* looks if zmask/hiz is in use and enables fastfill accordingly. */
if (zstex &&
(zstex->zmask_in_use[fb->zsbuf->u.tex.level] ||
zstex->hiz_in_use[fb->zsbuf->u.tex.level])) {
r300_mark_atom_dirty(r300, &r300->hyperz_state);
}
}
void r300_resume_query(struct r300_context *r300,
struct r300_query *query)
{
r300->query_current = query;
r300_mark_atom_dirty(r300, &r300->query_start);
}