static void r600_flush_from_st(struct pipe_context *ctx, struct pipe_fence_handle **fence, unsigned flags) { radeonsi_flush(ctx, fence, flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0); }
static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx, struct pipe_resource *texture, unsigned level, unsigned usage, const struct pipe_box *box) { struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; struct pipe_resource resource; struct r600_transfer *trans; int r; boolean use_staging_texture = FALSE; /* We cannot map a tiled texture directly because the data is * in a different order, therefore we do detiling using a blit. * * Also, use a temporary in GTT memory for read transfers, as * the CPU is much happier reading out of cached system memory * than uncached VRAM. */ if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED && rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR) use_staging_texture = TRUE; if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) use_staging_texture = TRUE; /* XXX: Use a staging texture for uploads if the underlying BO * is busy. No interface for checking that currently? so do * it eagerly whenever the transfer doesn't require a readback * and might block. */ if ((usage & PIPE_TRANSFER_WRITE) && !(usage & (PIPE_TRANSFER_READ | PIPE_TRANSFER_DONTBLOCK | PIPE_TRANSFER_UNSYNCHRONIZED))) use_staging_texture = TRUE; if (!permit_hardware_blit(ctx->screen, texture) || (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) use_staging_texture = FALSE; if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) return NULL; trans = CALLOC_STRUCT(r600_transfer); if (trans == NULL) return NULL; pipe_resource_reference(&trans->transfer.resource, texture); trans->transfer.level = level; trans->transfer.usage = usage; trans->transfer.box = *box; if (rtex->depth) { /* XXX: only readback the rectangle which is being mapped? */ /* XXX: when discard is true, no need to read back from depth texture */ r = r600_texture_depth_flush(ctx, texture, FALSE); if (r < 0) { R600_ERR("failed to create temporary texture to hold untiled copy\n"); pipe_resource_reference(&trans->transfer.resource, NULL); FREE(trans); return NULL; } trans->transfer.stride = rtex->flushed_depth_texture->surface.level[level].pitch_bytes; trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z); return &trans->transfer; } else if (use_staging_texture) { resource.target = PIPE_TEXTURE_2D; resource.format = texture->format; resource.width0 = box->width; resource.height0 = box->height; resource.depth0 = 1; resource.array_size = 1; resource.last_level = 0; resource.nr_samples = 0; resource.usage = PIPE_USAGE_STAGING; resource.bind = 0; resource.flags = R600_RESOURCE_FLAG_TRANSFER; /* For texture reading, the temporary (detiled) texture is used as * a render target when blitting from a tiled texture. */ if (usage & PIPE_TRANSFER_READ) { resource.bind |= PIPE_BIND_RENDER_TARGET; } /* For texture writing, the temporary texture is used as a sampler * when blitting into a tiled texture. */ if (usage & PIPE_TRANSFER_WRITE) { resource.bind |= PIPE_BIND_SAMPLER_VIEW; } /* Create the temporary texture. */ trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource); if (trans->staging_texture == NULL) { R600_ERR("failed to create temporary texture to hold untiled copy\n"); pipe_resource_reference(&trans->transfer.resource, NULL); FREE(trans); return NULL; } trans->transfer.stride = ((struct r600_resource_texture *)trans->staging_texture) ->surface.level[0].pitch_bytes; if (usage & PIPE_TRANSFER_READ) { r600_copy_to_staging_texture(ctx, trans); /* Always referenced in the blit. */ radeonsi_flush(ctx, NULL, 0); } return &trans->transfer; } trans->transfer.stride = rtex->surface.level[level].pitch_bytes; trans->transfer.layer_stride = rtex->surface.level[level].slice_size; trans->offset = r600_texture_get_offset(rtex, level, box->z); return &trans->transfer; }
static void *si_texture_transfer_map(struct pipe_context *ctx, struct pipe_resource *texture, unsigned level, unsigned usage, const struct pipe_box *box, struct pipe_transfer **ptransfer) { struct r600_context *rctx = (struct r600_context *)ctx; struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; struct r600_transfer *trans; boolean use_staging_texture = FALSE; struct radeon_winsys_cs_handle *buf; enum pipe_format format = texture->format; unsigned offset = 0; char *map; /* We cannot map a tiled texture directly because the data is * in a different order, therefore we do detiling using a blit. * * Also, use a temporary in GTT memory for read transfers, as * the CPU is much happier reading out of cached system memory * than uncached VRAM. */ if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED && rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR) use_staging_texture = TRUE; /* XXX: Use a staging texture for uploads if the underlying BO * is busy. No interface for checking that currently? so do * it eagerly whenever the transfer doesn't require a readback * and might block. */ if ((usage & PIPE_TRANSFER_WRITE) && !(usage & (PIPE_TRANSFER_READ | PIPE_TRANSFER_DONTBLOCK | PIPE_TRANSFER_UNSYNCHRONIZED))) use_staging_texture = TRUE; if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) use_staging_texture = FALSE; if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) return NULL; trans = CALLOC_STRUCT(r600_transfer); if (trans == NULL) return NULL; pipe_resource_reference(&trans->transfer.resource, texture); trans->transfer.level = level; trans->transfer.usage = usage; trans->transfer.box = *box; if (rtex->is_depth) { /* XXX: only readback the rectangle which is being mapped? */ /* XXX: when discard is true, no need to read back from depth texture */ struct r600_resource_texture *staging_depth; if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { R600_ERR("failed to create temporary texture to hold untiled copy\n"); pipe_resource_reference(&trans->transfer.resource, NULL); FREE(trans); return NULL; } si_blit_uncompress_depth(ctx, rtex, staging_depth, level, level, box->z, box->z + box->depth - 1); trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size; trans->offset = r600_texture_get_offset(staging_depth, level, box->z); trans->staging = &staging_depth->resource.b.b; } else if (use_staging_texture) { struct pipe_resource resource; struct r600_resource_texture *staging; memset(&resource, 0, sizeof(resource)); resource.format = texture->format; resource.width0 = box->width; resource.height0 = box->height; resource.depth0 = 1; resource.array_size = 1; resource.usage = PIPE_USAGE_STAGING; resource.flags = R600_RESOURCE_FLAG_TRANSFER; /* We must set the correct texture target and dimensions if needed for a 3D transfer. */ if (box->depth > 1 && util_max_layer(texture, level) > 0) resource.target = texture->target; else resource.target = PIPE_TEXTURE_2D; switch (resource.target) { case PIPE_TEXTURE_1D_ARRAY: case PIPE_TEXTURE_2D_ARRAY: case PIPE_TEXTURE_CUBE_ARRAY: resource.array_size = box->depth; break; case PIPE_TEXTURE_3D: resource.depth0 = box->depth; break; default:; } /* Create the temporary texture. */ staging = (struct r600_resource_texture*)ctx->screen->resource_create(ctx->screen, &resource); if (staging == NULL) { R600_ERR("failed to create temporary texture to hold untiled copy\n"); pipe_resource_reference(&trans->transfer.resource, NULL); FREE(trans); return NULL; } trans->staging = &staging->resource.b.b; trans->transfer.stride = staging->surface.level[0].pitch_bytes; trans->transfer.layer_stride = staging->surface.level[0].slice_size; if (usage & PIPE_TRANSFER_READ) { r600_copy_to_staging_texture(ctx, trans); /* Always referenced in the blit. */ radeonsi_flush(ctx, NULL, 0); } } else { trans->transfer.stride = rtex->surface.level[level].pitch_bytes; trans->transfer.layer_stride = rtex->surface.level[level].slice_size; trans->offset = r600_texture_get_offset(rtex, level, box->z); } if (trans->staging) { buf = si_resource(trans->staging)->cs_buf; } else { buf = rtex->resource.cs_buf; } if (rtex->is_depth || !trans->staging) offset = trans->offset + box->y / util_format_get_blockheight(format) * trans->transfer.stride + box->x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); if (!(map = rctx->ws->buffer_map(buf, rctx->cs, usage))) { pipe_resource_reference(&trans->staging, NULL); pipe_resource_reference(&trans->transfer.resource, NULL); FREE(trans); return NULL; } *ptransfer = &trans->transfer; return map + offset; }
static void r600_flush_from_winsys(void *ctx, unsigned flags) { radeonsi_flush((struct pipe_context*)ctx, NULL, flags); }