void wlan_agc_config(u32 ant_mode) {
//ant_mode argument allows per-antenna AGC settings, in case FMC module has different
// response than on-board RF interfaces. Testing so far indicates the settings below
// work fine for all RF interfaces
//Post Rx_done reset delays for [rxhp, g_rf, g_bb]
wlan_agc_set_reset_timing(4, 250, 250);
//AGC config:
//RFG Thresh 3->2, 2->1, Avg_len_sel, V_DB_Adj, Init G_BB
wlan_agc_set_config( (256-56), (256-37), 0, 6, 24);
//AGC RSSI->Rx power offsets
wlan_agc_set_RSSI_pwr_calib(100, 85, 70);
//AGC timing: capt_rssi_1, capt_rssi_2, capt_v_db, agc_done
wlan_agc_set_AGC_timing(1, 30, 90, 96);
//AGC timing: start_dco, en_iir_filt
wlan_agc_set_DCO_timing(100, (100+34));
//AGC target output power (log scale)
wlan_agc_set_target( (64-16) );
#if 0
xil_printf("Switching to MGC for ant %d\n", ant_id);
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_REG);
radio_controller_setRxHP(RC_BASEADDR, RC_ALL_RF, RC_RXHP_OFF);
radio_controller_setRxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_SPI);
//Set Rx gains
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXGAIN_RF, 3);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXGAIN_BB, 8);
#endif
return;
}
void wlan_tx_config_ant_mode(u32 ant_mode) {
return;
/*OLD - DELETE WHEN v40 HW WORKS!*/
REG_CLEAR_BITS(WLAN_TX_REG_CFG, (WLAN_TX_REG_CFG_ANT_A_TXEN | WLAN_TX_REG_CFG_ANT_B_TXEN | WLAN_TX_REG_CFG_ANT_C_TXEN | WLAN_TX_REG_CFG_ANT_D_TXEN));
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_TXEN_CTRLSRC, RC_CTRLSRC_REG);
switch(ant_mode) {
case TX_ANTMODE_SISO_ANTA:
REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_ANT_A_TXEN);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, RC_REG0_TXEN_CTRLSRC, RC_CTRLSRC_HW);
break;
case TX_ANTMODE_SISO_ANTB:
REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_ANT_B_TXEN);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFB, RC_REG0_TXEN_CTRLSRC, RC_CTRLSRC_HW);
break;
case TX_ANTMODE_SISO_ANTC:
REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_ANT_C_TXEN);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFC, RC_REG0_TXEN_CTRLSRC, RC_CTRLSRC_HW);
break;
case TX_ANTMODE_SISO_ANTD:
REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_ANT_D_TXEN);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFD, RC_REG0_TXEN_CTRLSRC, RC_CTRLSRC_HW);
break;
default:
//Default to SISO on A if user provides invalid mode
xil_printf("wlan_tx_config_ant_mode ERROR: Invalid Mode - Defaulting to SISO on A\n");
REG_SET_BITS(WLAN_TX_REG_CFG, WLAN_TX_REG_CFG_ANT_A_TXEN);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, RC_REG0_TXEN_CTRLSRC, RC_CTRLSRC_HW);
break;
}
return;
}
void wlan_radio_init() {
//Setup clocking and filtering (20MSps, 2x interp/decimate in AD9963)
clk_config_dividers(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));
ad_config_filters(AD_BASEADDR, AD_ALL_RF, 2, 2);
//Setup RFA
radio_controller_TxRxDisable(RC_BASEADDR, RC_ALL_RF);
radio_controller_apply_TxDCO_calibration(AD_BASEADDR, EEPROM_BASEADDR, (RC_RFA | RC_RFB));
#ifdef WLAN_4RF_EN
radio_controller_apply_TxDCO_calibration(AD_BASEADDR, FMC_EEPROM_BASEADDR, (RC_RFC | RC_RFD));
#endif
radio_controller_setCenterFrequency(RC_BASEADDR, RC_ALL_RF, RC_24GHZ, 4);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RSSI_HIGH_BW_EN, 0);
//Filter bandwidths
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXHPF_HIGH_CUTOFF_EN, 1);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXLPF_BW, 1);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLPF_BW, 1);
#if 0
//MGC
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_REG);
radio_controller_setRxHP(RC_BASEADDR, RC_ALL_RF, RC_RXHP_OFF);
radio_controller_setRxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_SPI);
//Set Rx gains
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXGAIN_RF, 1);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_RXGAIN_BB, 8);
#else
//AGC
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_HW);
radio_controller_setRxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_HW);
#endif
//Set Tx gains
//radio_controller_setTxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_REG); //Used for software control of gains
//radio_controller_setTxGainTarget(RC_BASEADDR, RC_ALL_RF, 45);
radio_controller_setTxGainSource(RC_BASEADDR, RC_ALL_RF, RC_GAINSRC_HW); //Used for hardware control of gains
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXGAIN_BB, 2);
//Set misc radio params
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLINEARITY_PADRIVER, 0);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLINEARITY_VGA, 0);
radio_controller_setRadioParam(RC_BASEADDR, RC_ALL_RF, RC_PARAMID_TXLINEARITY_UPCONV, 0);
//Set Tx state machine timing (dly_GainRamp, dly_PA, dly_TX, dly_PHY)
radio_controller_setTxDelays(RC_BASEADDR, 40, 20, 0, TX_RC_PHYSTART_DLY); //240 PA time after 180 PHY time is critical point
//Configure the radio_controller Tx/Rx enable control sources
// The Tx PHY drives a 4-bit TxEn, one bit per RF interface
// The Tx PHY drives a 1-bit RxEn, common to all RF interfaces
// MAC software should select active Rx interface by changing RFA/RFB RxEn ctrl src between _HW and _REG
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, (RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_HW);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFB, (RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFA | RC_RFB), (RC_REG0_TXEN_CTRLSRC), RC_CTRLSRC_HW);
//Disable any hardware control of RFC/RFD
radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFC | RC_RFD), (RC_REG0_RXEN_CTRLSRC | RC_REG0_TXEN_CTRLSRC), RC_CTRLSRC_REG);
/*
OLD - DELTE WHEN v40 HW WORKS
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_HW);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFB, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFC, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFD, (RC_REG0_TXEN_CTRLSRC | RC_REG0_RXEN_CTRLSRC), RC_CTRLSRC_REG);
*/
return;
}
void wlan_rx_config_ant_mode(u32 ant_mode) {
//Hold the Rx PHY in reset before changing any pkt det or radio enables
REG_SET_BITS(WLAN_RX_REG_CTRL, WLAN_RX_REG_CTRL_RESET);
//Disable all Rx modes first; selectively re-enabled in switch below
REG_CLEAR_BITS(WLAN_RX_REG_CFG, (
WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A |
WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B |
WLAN_RX_REG_CFG_PKT_DET_EN_ANT_C |
WLAN_RX_REG_CFG_PKT_DET_EN_ANT_D |
WLAN_RX_REG_CFG_SWITCHING_DIV_EN |
WLAN_RX_REG_CFG_PKT_DET_EN_EXT |
WLAN_RX_REG_CFG_ANT_SEL_MASK));
//Disable PHY control of all RF interfaces - selected interfaces to re-enabled below
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_REG);
switch(ant_mode) {
case RX_ANTMODE_SISO_ANTA:
//Enable packet detection on RF A
REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A);
//Select RF A I/Q stream for Rx PHY
wlan_phy_select_rx_antenna(0);
//Give PHY control of RF A Tx/Rx status
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_HW);
//Configure AGC for RF A
wlan_agc_config(RX_ANTMODE_SISO_ANTA);
break;
case RX_ANTMODE_SISO_ANTB:
REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B);
wlan_phy_select_rx_antenna(1);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFB, RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_HW);
wlan_agc_config(RX_ANTMODE_SISO_ANTB);
break;
case RX_ANTMODE_SISO_ANTC:
REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_C);
wlan_phy_select_rx_antenna(2);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFC, RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_HW);
wlan_agc_config(RX_ANTMODE_SISO_ANTC);
break;
case RX_ANTMODE_SISO_ANTD:
REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_D);
wlan_phy_select_rx_antenna(3);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFD, RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_HW);
wlan_agc_config(RX_ANTMODE_SISO_ANTD);
break;
case RX_ANTMODE_SISO_SELDIV_2ANT:
REG_SET_BITS(WLAN_RX_REG_CFG, (WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B | WLAN_RX_REG_CFG_SWITCHING_DIV_EN));
radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFA | RC_RFB), RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_HW);
wlan_agc_config(RX_ANTMODE_SISO_SELDIV_2ANT);
break;
case RX_ANTMODE_SISO_SELDIV_4ANT:
REG_SET_BITS(WLAN_RX_REG_CFG, (WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_C | WLAN_RX_REG_CFG_PKT_DET_EN_ANT_D | WLAN_RX_REG_CFG_SWITCHING_DIV_EN));
radio_controller_setCtrlSource(RC_BASEADDR, RC_ALL_RF, RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_HW);
wlan_agc_config(RX_ANTMODE_SISO_SELDIV_4ANT);
break;
default:
//Default to SISO on A if user provides invalid mode
xil_printf("wlan_rx_config_ant_mode ERROR: Invalid Mode - Defaulting to SISO on A\n");
REG_SET_BITS(WLAN_RX_REG_CFG, WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A);
wlan_phy_select_rx_antenna(0);
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, RC_REG0_RXEN_CTRLSRC, RC_CTRLSRC_HW);
wlan_agc_config(RX_ANTMODE_SISO_ANTA);
break;
}
//Release the PHY Rx reset
REG_CLEAR_BITS(WLAN_RX_REG_CTRL, WLAN_RX_REG_CTRL_RESET);
return;
}
int main(){
w3_node_init();
// Write some code here that gives a user instructions for controlling your transceiver.
// --- Enable/disable transmitter
// --- Enable/disable receiver
// --- Enable/disable/reset CFO Correction
// --- Enable/disable/reset timing correction
// --- Select output of DAC (to view signals at various stages in your design)
// --- Modify all filter coefficients (both for CFO and timing synchronization) for tuning
//Set up the UART
XUartLite_Initialize(&UartLite, XPAR_UARTLITE_0_DEVICE_ID);
//Set up the Radio - For details about these calls, see http://warp.rice.edu/svn/WARP/PlatformSupport/CustomPeripherals/pcores/radio_controller_v3_00_b/doc/html/api/index.html
// Configure TX enable, RX enable, and Rx HP filter for software control
radio_controller_setCtrlSource(RC_BASEADDR, RC_RFA, (RC_REG0_TXEN_CTRLSRC|RC_REG0_RXEN_CTRLSRC|RC_REG0_RXHP_CTRLSRC), RC_CTRLSRC_REG);
// Configure TX low-pass filter response to have a corner frequency of 18 MHz:
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXLPF_BW, 0x01);
//Enable software Tx Gain control:
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_TXGAINS_SPI_CTRL_EN, 0x01);
//Enable software Rx Gain control:
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_RXGAINS_SPI_CTRL_EN, 0x01);
//Initialize the baseband Tx gain to its max value (0 dB)
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_TXGAIN_BB, 0x00);
//Initialize the RF Tx gain
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_RF, TxGain);
// Configure receive HPF cutoff of 30kHz (DC block)
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXHPF_HIGH_CUTOFF_EN, 0x01);
//14MHz Low Pass Filter on RX (our max freq is 10MHz + 2.25MHz)
// 0: 7.5MHz<br>1: 9.5MHz<br>2: 14MHz<br>3: 18MHz
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXLPF_BW, 0x03);
//Initialize the Rx RF Gain (1:0dB, 2:15dB , 3:30dB )
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA,RC_PARAMID_RXGAIN_RF, RxCoarseGain);
//Initialize the Rx baseband Gain
radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_BB, RxFineGain);
// Enable the receiver by default
// Set center frequency (i.e. choose the WiFi channel)
radio_controller_setCenterFrequency(RC_BASEADDR , RC_RFA, RC_24GHZ, wifiChannel);
//DECLERATION OF VARIABLES
int x = 0; //Variable used for reading UART
Xuint32 dataIn; //Variable used to temporarily store data read from memory using the XIO_In32() function
Xuint32 dataOut; //Variable used to temporarily store data to write to memory using the XIO_Out32() function
XIo_Out32(Delay,43); //Write the desired value for the PA delay
radio_controller_RxEnable(RC_BASEADDR, RC_RFB); //Turn on Receiver RFB
radio_controller_TxEnable(RC_BASEADDR, RC_RFA); //Turn on Transmitter RFA
dataIn = XIo_In32(Delay); //Read in first delay for sanity check
xil_printf("first delay: %d \n \r", dataIn); //Print to terminal for user to look at
XIo_Out32(Controls,0x80000000); //Turn On LTE signal
while(1){
x = XUartLite_RecvByte(STDIN_BASEADDRESS); //Input from UART
////TURN TRAINING ON////
if(x=='t'){
XIo_Out32(Controls,0x04000000); //Turn Off Signal, DPD, learning, and reset
XIo_Out32(Controls,0xF0000000); //Turn On LTE, DPD, and Training
xil_printf("Training Activated \n \r");
}
////COMMANDS TO LOOK AT AND CHANGE DELAY////
if(x=='d'){ //Read current delay
dataIn = XIo_In32(Delay);
xil_printf("Current Delay: %d \n \r", dataIn);
}
if(x=='e'){ //Increase delay
radio_controller_TxRxDisable(RC_BASEADDR, RC_RFA|RC_RFB); //Turn off TX and RX RFB
XIo_Out32(Controls,0x04000000); //Turn Off LTE, DPD, Training, and Reset
dataIn = XIo_In32(Delay); //Read current delay
dataOut = dataIn + 1; //step by 1
XIo_Out32(Delay,dataOut); //Write to delay
dataIn = XIo_In32(Delay); //Read current delay
xil_printf("New Delay: %d \n \r", dataIn);
radio_controller_RxEnable(RC_BASEADDR, RC_RFB); //Turn on Receiver RFB
radio_controller_TxEnable(RC_BASEADDR, RC_RFA); //Turn on Transmitter RFA
XIo_Out32(Controls,0xF0000000); //Turn On LTE, DPD, and Training
}
if(x=='c'){ //Decrease delay
radio_controller_TxRxDisable(RC_BASEADDR, RC_RFA|RC_RFB); //Turn off TX and RX RFB
XIo_Out32(Controls,0x04000000); //Turn Off LTE, DPD, Training, and Reset
dataIn = XIo_In32(Delay); //Read current delay
dataOut = dataIn - 1; //step by 1
XIo_Out32(Delay,dataOut); //Write to delay
dataIn = XIo_In32(Delay); //Read current delay
xil_printf("New Delay: %d \n \r", dataIn);
radio_controller_RxEnable(RC_BASEADDR, RC_RFB); //Turn on Receiver RFB
radio_controller_TxEnable(RC_BASEADDR, RC_RFA); //Turn on Transmitter RFA
XIo_Out32(Controls,0xF0000000); //Turn On LTE, DPD, and Training
}
////REPORT ALL ALPHAS FROM TRAINING////
if(x=='l'){
int i = 0;
for(i = 0;i<Alpha_depth;i=i+4 ){
dataIn = XIo_In32(Alpha_memory+i); //Read alpha
xil_printf("%08x, address: %08x \n \r", dataIn, Alpha_memory+i);
}
}
////COMMANDS FOR CHANGING ALPHA MANUALLY///
if(x=='a'){ //Switch to Manual Alpha
XIo_Out32(Controls,0x04000000); //Turn Off Signal, DPD, learning, and reset
XIo_Out32(Controls,0xC8000000); //Turn On LTE, DPD, and manual alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("Current Alpha: %08x \n \r", dataIn);
}
if(x=='q'){ //Increase Manual Alpha Real
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn + 0x01000000; //step by 2^-6 = 0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
if(x=='z'){ //Decrease Manual Alpha Real
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn - 0x01000000; //step by -2^-6 = -0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
if(x=='w'){ //Increase Manual Alpha Imag
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn + 0x00000100; //step by 2^-6 = 0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
if(x=='x'){ //Decrease Manual Alpha Imag
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
dataOut = dataIn - 0x00000100; //step by -2^-6 = -0.015625
XIo_Out32(Alpha_user,dataOut); //Write to user defined alpha
dataIn = XIo_In32(Alpha_user); //Read current user defined alpha
xil_printf("New Alpha: %08x \n \r", dataIn);
}
}
}
