void rcc_clock_setup_hsi(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */ rcc_wait_for_sysclk_status(HSI); rcc_osc_off(PLL); rcc_wait_for_osc_not_ready(PLL); rcc_set_pll_source(clock->pllsrc); rcc_set_main_pll_hsi(clock->pll); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre2(clock->ppre2); rcc_set_ppre1(clock->ppre1); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */ /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; }
static inline void rcc_clock_setup_hse(const my_clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); /* Select HSE as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSE); rcc_wait_for_sysclk_status(HSE); rcc_osc_off(PLL); rcc_wait_for_osc_not_ready(PLL); rcc_set_pll_source(clock->pllsrc); rcc_set_main_pll_hse(clock->pll); RCC_CFGR2 = (clock->pllpre << RCC_CFGR2_PREDIV_SHIFT); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_hpre(clock->hpre); rcc_set_ppre2(clock->ppre2); rcc_set_ppre1(clock->ppre1); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
static void clk_tree_setup(void) { /* cf. rcc_clock_setup_in_hsi_out_48mhz */ rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); rcc_set_sysclk_source(RCC_HSI); rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); rcc_osc_off(RCC_PLL); rcc_wait_for_osc_not_ready(RCC_PLL); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); #ifdef NUCLEO rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6); #else /* 16MHz * 3 = 48MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL3); #endif rcc_set_pll_source(RCC_HSE); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); rcc_apb1_frequency = 48000000UL; rcc_ahb_frequency = 48000000UL; rcc_set_usbclk_source(RCC_PLL); }
/* Set the clock to max speed. */ static void clock_setup(void) { #if defined(STM32F0) rcc_clock_setup_in_hsi_out_48mhz(); #elif defined(STM32L0) /* After a reset, the system uses [email protected]. */ /* end result: 32MHz PLLVCO from HSI16, * no system/periph clock divide. */ /* increase the latency to 1 wait state (we'll be speeding up) */ flash_set_ws(1); /* turn on HSI16 */ rcc_osc_on(RCC_HSI16); rcc_wait_for_osc_ready(RCC_HSI16); /* run AHB, APB1, APB2 at full speed */ rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV); rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV); /* turn off PLL and wait for it to fully stop */ rcc_osc_off(RCC_PLL); while (RCC_CR & RCC_CR_PLLRDY); /* set PLL source to HSI16 */ RCC_CFGR &= ~(1<<16); // RCC_CFGR_PLLSRC /* set up PLL */ rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL4); rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2); /* turn on and switch to PLL */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); rcc_ahb_frequency = 32000000; rcc_apb1_frequency = 32000000; rcc_apb2_frequency = 32000000; #else #error "Implement a clock setup." #endif }
static void rcc_clock_setup_pll_f3_special(const rcc_clock_scale_t *clock) { /* Turn on the appropriate source for the PLL */ // TODO, some f3's have extra bits here enum rcc_osc my_osc; if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_PREDIV) { my_osc = RCC_HSE; } else { my_osc = RCC_HSI; } rcc_osc_on(my_osc); while (!rcc_is_osc_ready(my_osc)); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_osc_off(RCC_PLL); while (rcc_is_osc_ready(RCC_PLL)); rcc_set_pll_source(clock->pll_source); rcc_set_pll_multiplier(clock->pll_mul); // TODO - iff pll_div != 0, then maybe we're on a target that // has the dividers? /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); while (!rcc_is_osc_ready(RCC_PLL)); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); rcc_wait_for_sysclk_status(RCC_PLL); /* Set the peripheral clock frequencies used. */ rcc_ahb_frequency = clock->ahb_frequency; rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
/** * Setup clocks to run from PLL. * The arguments provide the pll source, multipliers, dividers, all that's * needed to establish a system clock. * @param clock clock information structure */ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { if (clock->pllsrc == RCC_CFGR_PLLSRC_HSE_PREDIV) { rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); } else { rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); } rcc_osc_off(RCC_PLL); rcc_usb_prescale_1_5(); if (clock->usbdiv1) { rcc_usb_prescale_1(); } rcc_wait_for_osc_not_ready(RCC_PLL); rcc_set_pll_source(clock->pllsrc); rcc_set_pll_multiplier(clock->pllmul); rcc_set_prediv(clock->plldiv); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Configure flash settings. */ flash_prefetch_enable(); flash_set_ws(clock->flash_waitstates); rcc_set_hpre(clock->hpre); rcc_set_ppre2(clock->ppre2); rcc_set_ppre1(clock->ppre1); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(RCC_PLL); /* Set the peripheral clock frequencies used. */ rcc_ahb_frequency = clock->ahb_frequency; rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
/** * Set up sysclock with PLL from HSI16 * @param clock full struct with desired parameters */ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { /* Turn on the appropriate source for the PLL */ if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); } else { rcc_osc_on(RCC_HSI16); rcc_wait_for_osc_ready(RCC_HSI16); } rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_periph_clock_enable(RCC_PWR); pwr_set_vos_scale(clock->voltage_scale); rcc_osc_off(RCC_PLL); while (rcc_is_osc_ready(RCC_PLL)); flash_prefetch_enable(); flash_set_ws(clock->flash_waitstates); /* Set up the PLL */ rcc_set_pll_multiplier(clock->pll_mul); rcc_set_pll_divider(clock->pll_div); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); /* Set the peripheral clock frequencies used. */ rcc_ahb_frequency = clock->ahb_frequency; rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
void clock_setup() { /* RCC_CR |= (uint32_t)0x00000001; RCC_CFGR = 0x00000000; RCC_CR &= (uint32_t)0xFEF6FFFF; RCC_PLLCFGR = 0x24003010; RCC_CR &= (uint32_t)0xFFFBFFFF; RCC_CIR = 0x00000000; SCB_VTOR = 0x08000000; */ /* .pllm = 16, .plln = 336, .pllp = 2, .pllq = 7, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS, .apb1_frequency = 42000000, .apb2_frequency = 84000000, */ /* Enable internal high-speed oscillator. */ rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); pwr_set_vos_scale(PWR_SCALE1); rcc_set_main_pll_hsi(16, 336, 2, 8, 0); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Configure flash settings. */ flash_set_ws(FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE); rcc_set_ppre1(RCC_CFGR_PPRE_DIV_4); rcc_set_ppre2(RCC_CFGR_PPRE_DIV_2); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(RCC_PLL); rcc_ahb_frequency = 168000000; rcc_apb1_frequency = 42000000; rcc_apb2_frequency = 84000000; /* Disable internal high-speed oscillator. */ rcc_osc_off(RCC_HSI); // clock rate is 1680 to get 10uS interrupt rate systick_set_reload(168); systick_set_clocksource(STK_CSR_CLKSOURCE_AHB); systick_counter_enable(); systick_interrupt_enable(); rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); etk::set_tick_rate(1); }
void gpio_setup(void) { rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); rcc_osc_off(RCC_PLL); rcc_wait_for_osc_not_ready(RCC_PLL); rcc_set_prediv(RCC_CFGR2_PREDIV_NODIV); rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_PREDIV); rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_PLL_IN_CLK_X3); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE); rcc_set_ppre2(RCC_CFGR_PPRE1_DIV_2); rcc_set_ppre1(RCC_CFGR_PPRE2_DIV_NONE); flash_set_ws(FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS); rcc_set_sysclk_source(RCC_CFGR_SW_PLL); rcc_wait_for_sysclk_status(RCC_PLL); rcc_ahb_frequency = 60000000; rcc_apb1_frequency = 30000000; rcc_apb2_frequency = 30000000; rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); rcc_periph_clock_enable(RCC_GPIOD); rcc_periph_clock_enable(RCC_GPIOE); rcc_periph_clock_enable(RCC_USART1); rcc_periph_clock_enable(RCC_TIM2); rcc_periph_clock_enable(RCC_DAC1); nvic_enable_irq(NVIC_TIM1_CC_IRQ); nvic_enable_irq(NVIC_TIM2_IRQ); nvic_enable_irq(NVIC_TIM3_IRQ); nvic_enable_irq(NVIC_ADC1_2_IRQ); /* Unused pins. */ gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO0 | GPIO2 | GPIO6 | GPIO11 | GPIO12 ); gpio_mode_setup(GPIOB, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO0 | GPIO1 | GPIO2 | GPIO6 | GPIO7 | GPIO8 | GPIO10 | GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15 ); gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO6 | GPIO7 | GPIO8 | GPIO13 ); gpio_mode_setup(GPIOD, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO6 | GPIO7 | GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15 ); gpio_mode_setup(GPIOE, GPIO_MODE_INPUT, GPIO_PUPD_PULLDOWN, GPIO0 | GPIO1 | GPIO3 | GPIO4 | GPIO7 | GPIO8 | GPIO10 | GPIO11 | GPIO12 | GPIO13 | GPIO14 ); // gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5); gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3); /* Timer 2, IC2 */ gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO1); gpio_set_af(GPIOA, GPIO_AF1, GPIO1); /* USART2 */ gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO9 | GPIO10); gpio_set_af(GPIOA, GPIO_AF7, GPIO9 | GPIO10); /* ADC1, channel 4, no filter, fast channel. */ gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO3); /* ADC2, channel 4, no filter, fast channel. */ gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO7); /* ADC3, channel 2, no filter, fast channel. */ gpio_mode_setup(GPIOE, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO9); /* ADC4, channel 2, no filter, fast channel. */ gpio_mode_setup(GPIOE, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO15); /* VCTCXO steering, DAC output. */ gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4); }