static inline void rcc_clock_setup_hse(const my_clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSE); rcc_wait_for_osc_ready(HSE); /* Select HSE as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSE); rcc_wait_for_sysclk_status(HSE); rcc_osc_off(PLL); rcc_wait_for_osc_not_ready(PLL); rcc_set_pll_source(clock->pllsrc); rcc_set_main_pll_hse(clock->pll); RCC_CFGR2 = (clock->pllpre << RCC_CFGR2_PREDIV_SHIFT); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_hpre(clock->hpre); rcc_set_ppre2(clock->ppre2); rcc_set_ppre1(clock->ppre1); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
static void clk_tree_setup(void) { /* cf. rcc_clock_setup_in_hsi_out_48mhz */ rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); rcc_set_sysclk_source(RCC_HSI); rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); rcc_osc_off(RCC_PLL); rcc_wait_for_osc_not_ready(RCC_PLL); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); #ifdef NUCLEO rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6); #else /* 16MHz * 3 = 48MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL3); #endif rcc_set_pll_source(RCC_HSE); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); rcc_apb1_frequency = 48000000UL; rcc_ahb_frequency = 48000000UL; rcc_set_usbclk_source(RCC_PLL); }
void rcc_clock_setup_hsi(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */ rcc_wait_for_sysclk_status(HSI); rcc_osc_off(PLL); rcc_wait_for_osc_not_ready(PLL); rcc_set_pll_source(clock->pllsrc); rcc_set_main_pll_hsi(clock->pll); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre2(clock->ppre2); rcc_set_ppre1(clock->ppre1); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */ /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre2_frequency = clock->apb2_frequency; }
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 8MHz. */ rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set the PLL multiplication factor to 9. * 8MHz (external) * 9 (multiplier) = 72MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); /* Select HSE as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * External frequency undivided before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ahb_frequency = 72000000; rcc_apb1_frequency = 36000000; rcc_apb2_frequency = 72000000; }
void rcc_clock_setup_in_hse_25mhz_out_72mhz(void) { /* Enable external high-speed oscillator 25MHz. */ rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Sysclk runs with 72MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_2WS); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* Set pll2 prediv and multiplier */ rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5); rcc_set_pll2_multiplication_factor(RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8); /* Enable PLL2 oscillator and wait for it to stabilize */ rcc_osc_on(RCC_PLL2); rcc_wait_for_osc_ready(RCC_PLL2); /* Set pll1 prediv/multiplier, prediv1 src, and usb predivider */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); rcc_set_prediv1_source(RCC_CFGR2_PREDIV1SRC_PLL2_CLK); rcc_set_prediv1(RCC_CFGR2_PREDIV_DIV5); rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL9); rcc_set_pll_source(RCC_CFGR_PLLSRC_PREDIV1_CLK); rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3); /* enable PLL1 and wait for it to stabilize */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ahb_frequency = 72000000; rcc_apb1_frequency = 36000000; rcc_apb2_frequency = 72000000; }
static void rcc_clock_setup_in_hse_12mhz_out_120mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* Enable external high-speed oscillator 12MHz. */ rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 120MHz Max. 108MHz */ RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_ADCPRE) | RCC_GCFGR_ADCPS_DIV12; /* ADC Set. 10MHz Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 60MHz Max. 54MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 120MHz Max. 108MHz */ RCC_CFGR |= RCC_GCFGR_USBPS_Div2_5; /* USB Set. 48MHz Max. 48MHz */ /* GD32 has 0-wait-state flash, do not touch anything! */ /* * Set the PLL multiplication factor to 10. * 12MHz (external) * 10 (multiplier) = 120MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL10); /* Select HSE as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); /* * External frequency undivided before entering PLL * (only valid/needed for HSE). */ rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ahb_frequency = 120000000; rcc_apb1_frequency = 60000000; rcc_apb2_frequency = 120000000; }
void clocksource_hse_in_8_out_48(void) { // see // https://www.mikrocontroller.net/attachment/322047/Clock_Control.png // or RM00091 p. 98 // enable internal high-speed oscillator rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); // Select HSI as SYSCLK source. rcc_set_sysclk_source(RCC_CFGR_SW_HSI); // Enable external high-speed oscillator 8MHz rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); rcc_set_sysclk_source(RCC_CFGR_SW_HSE); // set prescalers for AHB, ADC, ABP1, ABP2. // Do this before touching the PLL rcc_set_hpre(RCC_CFGR_HPRE_NODIV); // 48Mhz (max 72) rcc_set_ppre(RCC_CFGR_PPRE_DIV2); // 24Mhz (max 36) // sysclk runs with 48MHz -> 1 waitstates. // * 0WS from 0-24MHz // * 1WS from 24-48MHz // * 2WS from 48-72MHz flash_set_ws(FLASH_ACR_LATENCY_1WS); // set the PLL multiplication factor to 6 // pll source is hse RCC_CFGR |= RCC_CFGR_PLLSRC; // pll prediv = 1 rcc_set_prediv(RCC_CFGR2_PREDIV_NODIV); // 8MHz (external) * 6 (multiplier) = 48MHz rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6); // enable PLL oscillator and wait for it to stabilize. rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); // select PLL as SYSCLK source. rcc_set_sysclk_source(RCC_PLL); // set the peripheral clock frequencies used */ rcc_ahb_frequency = 48000000; rcc_apb1_frequency = 24000000; // When PPRE is set to something != NODIV // TIM input clock is apb clkspeed*2 (see RM00091 p98) rcc_timer_frequency = 2*rcc_apb1_frequency; }
void rcc_clock_setup_in_hsi_out_48mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /*Set.48MHz Max.72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /*Set. 6MHz Max.14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /*Set.24MHz Max.36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /*Set.48MHz Max.72MHz */ rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /*Set.48MHz Max.48MHz */ /* * Sysclk runs with 48MHz -> 1 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_ACR_LATENCY_1WS); /* * Set the PLL multiplication factor to 12. * 8MHz (internal) * 12 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 48MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL12); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used */ rcc_ahb_frequency = 48000000; rcc_apb1_frequency = 24000000; rcc_apb2_frequency = 48000000; }
/* Set STM32 to 32 MHz. */ static void clock_setup(void) { /* Enable PWR clock. */ rcc_enable_clock(RCC_PWR); /* Set VCORE to 1.8V */ pwr_set_vos(PWR_1_8_V); /* Enable 64bit flash memory access (1WS). */ flash_enable_64bit_access(1); /* Enable external high-speed oscillator 8MHz. */ rcc_enable_osc(RCC_HSE); /* Setup PLL (8MHz * 12 / 3 = 32MHz). */ rcc_setup_pll(RCC_HSE, 12, 3); /* AHB, APB1 and APB2 prescaler value is default. */ // rcc_set_prescaler(1, 1, 1); /* Enable PLL and wait for it to stabilize. */ rcc_enable_osc(RCC_PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_PLL); }
void rcc_clock_setup_hsi(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN); pwr_set_vos_scale(clock->voltage_scale); /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Set the peripheral clock frequencies used. */ rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
void rcc_clock_setup_hsi16(const struct rcc_clock_scale *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(RCC_HSI16); rcc_wait_for_osc_ready(RCC_HSI16); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI16); /* Enable/disable high performance mode */ pwr_set_vos_range(clock->voltage_scale); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Set the peripheral clock frequencies used. */ rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; rcc_set_msi_range(clock->msi_range); }
/* Set STM32 to 16 MHz. */ static void clock_setup(void) { /* Enable PWR clock. */ rcc_enable_clock(RCC_PWR); /* Set VCORE to 1.8V */ pwr_set_vos(PWR_1_8_V); /* * Set Flash memory latency. * * VCORE=1.8V VCORE=1.5V VCORE=1.2V * 0WS from 0-16MHz 0-8MHz 0-2MHz * 1WS from 16-32MHz 8-16MHz 2-4MHz */ flash_enable_64bit_access(0); /* Enable internal high-speed oscillator (16MHz). */ rcc_enable_osc(RCC_HSI); /* * APB2 16MHz (Max. 32MHz) * APB1 16MHz (Max. 32MHz) * AHB 16MHz (Max. 32MHz) */ /* AHB, APB1 and APB2 prescaler value is default. */ // rcc_set_prescaler(1, 1, 1); /* Select SYSCLK source. */ rcc_set_sysclk_source(RCC_HSI); }
void rcc_clock_setup_hsi_3v3(const clock_scale_t *clock) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); // /* Enable/disable high performance mode */ // if (!clock->power_save) { // pwr_set_vos_scale(SCALE1); // } else { // pwr_set_vos_scale(SCALE2); // } /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_set_main_pll_hsi(clock->pllm, clock->plln, clock->pllp, clock->pllq); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(PLL); /* Set the peripheral clock frequencies used. */ rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; /* Disable internal high-speed oscillator. */ //rcc_osc_off(HSI); }
void PWR_Shutdown() { printf("Shutdown\n"); BACKLIGHT_Brightness(0); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); rcc_wait_for_osc_ready(HSI); while(1) ; }
/* * These functions are setting up the whole clock system for the most common * input clock and output clock configurations. */ void rcc_clock_setup_in_hsi_out_64mhz(void) { /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */ rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Max. 14MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */ /* * Sysclk is running with 64MHz -> 2 waitstates. * 0WS from 0-24MHz * 1WS from 24-48MHz * 2WS from 48-72MHz */ flash_set_ws(FLASH_LATENCY_2WS); /* * Set the PLL multiplication factor to 16. * 8MHz (internal) * 16 (multiplier) / 2 (PLLSRC_HSI_CLK_DIV2) = 64MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL16); /* Select HSI/2 as PLL source. */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); }
/** * Set System Clock PLL at 48MHz from HSI */ void rcc_clock_setup_in_hsi_out_48mhz(void) { rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); rcc_set_sysclk_source(RCC_HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_prefetch_enable(); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); /* 8MHz * 12 / 2 = 48MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12); rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); rcc_apb1_frequency = 48000000; rcc_ahb_frequency = 48000000; }
int main(void) { /* Enable HSE */ rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); /* setup PLL */ // 8Mhz *8/2 -> 32MHz rcc_set_pll_source(RCC_HSE); rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL8); rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* switch to PLL */ rcc_set_sysclk_source(RCC_PLL); /* setup AHB/APBx */ rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV); rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV); gpio_setup(); systick_setup(2); /* init switch */ gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO12); gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO11); gpio_clear(GPIOA, GPIO11); /* get value */ gpio_get(GPIOA, GPIO12); while (1) { /* delay(); gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN); delay_short(); gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN); delay_short(); gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN); delay_short(); gpio_toggle(LED_GREEN_PORT, LED_GREEN_PIN); delay_short(); */ } return 0; }
void rcc_clock_setup_in_hsi_out_16mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ); /* 8MHz * 4 / 2 = 16MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4); RCC_CFGR &= ~RCC_CFGR_PLLSRC; rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); rcc_apb1_frequency = 16000000; rcc_ahb_frequency = 16000000; }
void cdcacm_target_init(void) { /* start HSI48 */ rcc_clock_setup_in_hsi48_out_48mhz(); /* use usb SOF as correction source for HSI48 */ crs_autotrim_usb_enable(); /* use HSI48 for USB */ rcc_set_usbclk_source(RCC_HSI48); /* usb HSI48 for system clock */ rcc_set_sysclk_source(RCC_HSI48); }
void rcc_clock_setup_in_hsi_out_8mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_000_024MHZ); rcc_ppre_frequency = 8000000; rcc_core_frequency = 8000000; }
void rcc_clock_setup_in_hsi_out_48mhz(void) { rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); rcc_set_sysclk_source(HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); /* 8MHz * 12 / 2 = 24MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL16); RCC_CFGR &= RCC_CFGR_PLLSRC; rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); rcc_ppre_frequency = 48000000; rcc_core_frequency = 48000000; }
void rcc_clock_setup_in_hsi_out_40mhz(void) { rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); rcc_set_sysclk_source(RCC_HSI); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); /* 8MHz * 10 / 2 = 40MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10); RCC_CFGR &= ~RCC_CFGR_PLLSRC; rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); rcc_apb1_frequency = 40000000; rcc_ahb_frequency = 40000000; }
void rcc_clock_setup_in_hsi48_out_48mhz(void) { rcc_osc_on(RCC_HSI48); rcc_wait_for_osc_ready(RCC_HSI48); rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre(RCC_CFGR_PPRE_NODIV); flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); rcc_set_sysclk_source(RCC_HSI48); rcc_apb1_frequency = 48000000; rcc_ahb_frequency = 48000000; }
/* Set the clock to max speed. */ static void clock_setup(void) { #if defined(STM32F0) rcc_clock_setup_in_hsi_out_48mhz(); #elif defined(STM32L0) /* After a reset, the system uses [email protected]. */ /* end result: 32MHz PLLVCO from HSI16, * no system/periph clock divide. */ /* increase the latency to 1 wait state (we'll be speeding up) */ flash_set_ws(1); /* turn on HSI16 */ rcc_osc_on(RCC_HSI16); rcc_wait_for_osc_ready(RCC_HSI16); /* run AHB, APB1, APB2 at full speed */ rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV); rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV); /* turn off PLL and wait for it to fully stop */ rcc_osc_off(RCC_PLL); while (RCC_CR & RCC_CR_PLLRDY); /* set PLL source to HSI16 */ RCC_CFGR &= ~(1<<16); // RCC_CFGR_PLLSRC /* set up PLL */ rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL4); rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2); /* turn on and switch to PLL */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); rcc_ahb_frequency = 32000000; rcc_apb1_frequency = 32000000; rcc_apb2_frequency = 32000000; #else #error "Implement a clock setup." #endif }
static void rcc_clock_setup_pll_f3_special(const rcc_clock_scale_t *clock) { /* Turn on the appropriate source for the PLL */ // TODO, some f3's have extra bits here enum rcc_osc my_osc; if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_PREDIV) { my_osc = RCC_HSE; } else { my_osc = RCC_HSI; } rcc_osc_on(my_osc); while (!rcc_is_osc_ready(my_osc)); /* Configure flash settings. */ flash_set_ws(clock->flash_config); /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_osc_off(RCC_PLL); while (rcc_is_osc_ready(RCC_PLL)); rcc_set_pll_source(clock->pll_source); rcc_set_pll_multiplier(clock->pll_mul); // TODO - iff pll_div != 0, then maybe we're on a target that // has the dividers? /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); while (!rcc_is_osc_ready(RCC_PLL)); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); rcc_wait_for_sysclk_status(RCC_PLL); /* Set the peripheral clock frequencies used. */ rcc_ahb_frequency = clock->ahb_frequency; rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { /* Turn on the appropriate source for the PLL */ if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); } else { rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); } /* * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_periph_clock_enable(RCC_PWR); pwr_set_vos_scale(clock->voltage_scale); /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ flash_set_ws(clock->flash_config); rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); /* Set the peripheral clock frequencies used. */ rcc_ahb_frequency = clock->ahb_frequency; rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
int main(void) { int32_t i; rcc_periph_clock_enable(RCC_GPIOA); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO5); flash_set_ws(FLASH_ACR_LATENCY_2WS); rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV4); /* 14MHz */ rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* 56MHz */ rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* 28MHz */ rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* 56MHz */ rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL14); /* 8MHz/2 x14 = 56MHz */ rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); rcc_osc_on(PLL); rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); rcc_periph_clock_enable(RCC_USART2); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_USART2_TX); gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_USART2_RX); uint32_t baud = 57600; uint32_t clock = 28000000; USART2_BRR = ((2 * clock) + baud) / (2 * baud); usart_set_databits(USART2, 8); usart_set_stopbits(USART2, USART_STOPBITS_1); usart_set_mode(USART2, USART_MODE_TX_RX); usart_set_parity(USART2, USART_PARITY_NONE); usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); usart_enable(USART2); usart_puts(USART2, "ready to receive.\r\n"); gpio_set(GPIOA, GPIO5); while(1) { uint16_t c; c = usart_recv_blocking(USART2); usart_send_blocking(USART2, toupper(c)); gpio_toggle(GPIOA, GPIO5); } }
void clock_init(void) { /* Enable HSE */ rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); /* setup PLL */ // 8Mhz *8/2 -> 32MHz rcc_set_pll_source(RCC_HSE); rcc_set_pll_multiplier(RCC_CFGR_PLLMUL_MUL8); rcc_set_pll_divider(RCC_CFGR_PLLDIV_DIV2); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* switch to PLL */ rcc_set_sysclk_source(RCC_PLL); /* setup AHB/APBx */ rcc_set_hpre(RCC_CFGR_HPRE_NODIV); rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV); rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV); }
/** * Setup clocks to run from PLL. * The arguments provide the pll source, multipliers, dividers, all that's * needed to establish a system clock. * @param clock clock information structure */ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { if (clock->pllsrc == RCC_CFGR_PLLSRC_HSE_PREDIV) { rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); } else { rcc_osc_on(RCC_HSI); rcc_wait_for_osc_ready(RCC_HSI); } rcc_osc_off(RCC_PLL); rcc_usb_prescale_1_5(); if (clock->usbdiv1) { rcc_usb_prescale_1(); } rcc_wait_for_osc_not_ready(RCC_PLL); rcc_set_pll_source(clock->pllsrc); rcc_set_pll_multiplier(clock->pllmul); rcc_set_prediv(clock->plldiv); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); /* Configure flash settings. */ flash_prefetch_enable(); flash_set_ws(clock->flash_waitstates); rcc_set_hpre(clock->hpre); rcc_set_ppre2(clock->ppre2); rcc_set_ppre1(clock->ppre1); /* Select PLL as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ rcc_wait_for_sysclk_status(RCC_PLL); /* Set the peripheral clock frequencies used. */ rcc_ahb_frequency = clock->ahb_frequency; rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }
/** * Set up sysclock with PLL from HSI16 * @param clock full struct with desired parameters */ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { /* Turn on the appropriate source for the PLL */ if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { rcc_osc_on(RCC_HSE); rcc_wait_for_osc_ready(RCC_HSE); } else { rcc_osc_on(RCC_HSI16); rcc_wait_for_osc_ready(RCC_HSI16); } rcc_set_hpre(clock->hpre); rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); rcc_periph_clock_enable(RCC_PWR); pwr_set_vos_scale(clock->voltage_scale); rcc_osc_off(RCC_PLL); while (rcc_is_osc_ready(RCC_PLL)); flash_prefetch_enable(); flash_set_ws(clock->flash_waitstates); /* Set up the PLL */ rcc_set_pll_multiplier(clock->pll_mul); rcc_set_pll_divider(clock->pll_div); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); rcc_set_sysclk_source(RCC_PLL); /* Set the peripheral clock frequencies used. */ rcc_ahb_frequency = clock->ahb_frequency; rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; }