/* * Read the IO Port. * * Input: * regType - Register Type * ioIndex - When register type is OTHER_REGISTER, then ioIndex should * contains the IO Port address. This will function just as * regular IO port reading. */ unsigned char peekIO( reg_type_t regType, /* Register Type */ unsigned short ioIndex /* IO Port Index */ ) { unsigned char value; switch (regType) { case MISCELLANEOUS_REGISTER: value = readIO(0x3CC); break; case SEQUENCER_REGISTER: writeIO(0x3C4, (unsigned char) ioIndex); value = readIO(0x3C5); break; case CRT_REGISTER: writeIO(0x3D4, (unsigned char) ioIndex); value = readIO(0x3D5); break; case GRAPHICS_REGISTER: writeIO(0x3CE, (unsigned char) ioIndex); value = readIO(0x3CF); break; default: value = readIO(ioIndex); break; } return (value); }
unsigned char readCharFromMem(int loc) { loc&=0xFFFF; /*if(loc == 0xFFA6){ printf("reading the value\n"); }*/ //return gbcMainMem[loc]; if(loc<0x4000) { //Rom Bank 00 always this one //printf("romBanks: 0x%p\n",romBanks); return romBanks[loc]; } else if(loc<0x8000) { //Other ROM banks, switchable return romBanks[(loc-0x4000)+0x4000*currentRomBank]; } else if(loc<0xA000) { //8KB Video Ram, 2 Banks, switchable return vramBanks[(loc-0x8000)+0x2000*currentVramBank]; } else if(loc<0xC000) { //External RAM, switchable return ramBanks[(loc-0xA000)+currentRamBank*0x2000]; } else if(loc<0xD000) { //Work Ram Bank 0, fixed return workBanks[(loc-0xC000)]; } else if(loc<0xE000) { //Work Ram Bank 1-7, switchable return workBanks[(loc-0xD000)+0x1000*currentWorkBank]; } else if(loc<0xFE00) { return readCharFromMem(loc-0x2000); } else if(loc<0xFEA0) { return OAMTable[loc-0xFE00]; } else if(loc<0xFF00) { return 0; } else if(loc<0xFF80) { return readIO(loc); } else if(loc<0xFFFF) { return hram[loc-0xFF80]; } else { return interruptER; } }
void spiInit(void) { #warning spi stuff is currently disabled #if 0 /* set SS, SCLK and MOSI to output mode, and MISO to input mode */ writeIO(&DDR_SPI, SPI_ALL, SPI_ALL ^ SPI_MISO); writeIO(&PORT_SPI, SPI_SS_NULL, SPI_SS_NULL); /* ensure that all slave select pins are high */ spiUnselect(); /* disable power saving for SPI, and enable hardware SPI with interrupts * disabled and master mode enabled */ writeIO(&PRR0, _BV(PRSPI), 0); writeIO(&SPCR, _BV(SPE) | _BV(MSTR), _BV(SPE) | _BV(MSTR)); /* read the status and data registers to clear the state */ readIO(&SPSR, 0xff); readIO(&SPDR, 0xff); #endif }
uint8_t MMU::Read(const uint16_t location) { // 0000 - 0100 => Bootstrap ROM (only if turned on) if (usingBootstrap && location < 0x0100) { return bootstrap[location]; } if (location < 0x8000) { return rom->controller->Read(location); } // 8000 - 9fff => VRAM bank (switchable in GBC) if (location < 0xa000) { return gpu->VRAM[gpu->VRAMbankId].bytes[location - 0x8000]; } // a000 - bfff => External RAM (switchable) if (location < 0xc000) { return rom->controller->Read(location); } // c000 - cfff => Work RAM fixed bank if (location < 0xd000) { return WRAM.bytes[location - 0xc000]; } // d000 - dfff => Switchable Work RAM bank if (location < 0xe000) { return WRAMbanks[WRAMbankId].bytes[location - 0xd000]; } // e000 - fdff => Mirror of c000 - ddff if (location < 0xfe00) { return Read(location - 0x2000); } // fe00 - fe9f => Sprite attribute table if (location < 0xfea0) { // Get OAM item uint8_t index = location / 4; OAMBlock block = gpu->sprites[index]; // Get requested byte uint8_t offset = location % 4; switch (offset) { case 0: return block.x; case 1: return block.y; case 2: return block.pattern; case 3: return block.flags.raw; default: throw std::logic_error("Bad OAM offset"); } } // fea0 - feff => Not usable if (location < 0xff00) { return 0; } // ff00 - ff7f => I/O Registers if (location < 0xff80) { return readIO(location - 0xff00); } // ff80 - fffe => High RAM (HRAM) if (location < 0xffff) { return ZRAM.bytes[location - 0xff80]; } // ffff => Interrupt mask return interruptEnable.raw; }