static void __init msp_smtc_smp_setup(void)
{
/*
* we won't get the definitive value until
* we've run smtc_prepare_cpus later, but
*/
if (read_c0_config3() & (1 << 2))
smp_num_siblings = smtc_build_cpu_map(0);
}
/*
* Platform SMP pre-initialization
*/
static void ssmtc_prepare_cpus(unsigned int max_cpus)
{
/*
* As noted above, we can assume a single CPU for now
* but it may be multithreaded.
*/
if (read_c0_config3() & (1 << 2)) {
mipsmt_prepare_cpus();
}
}
phys_t __mips_cm_phys_base(void)
{
u32 config3 = read_c0_config3();
u32 cmgcr;
/* Check the CMGCRBase register is implemented */
if (!(config3 & MIPS_CONF3_CMGCR))
return 0;
/* Read the address from CMGCRBase */
cmgcr = read_c0_cmgcrbase();
return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
}
PUBLIC
void
Jdb_kern_info_cpu::dump_cp0_regs()
{
Mword val;
DUMP_CP0("EBase", read_c0_ebase(), val);
DUMP_INT("Ebase.CPUNum", (val & 0x3ff));
DUMP_CP0("EntryHi", read_c0_entryhi(), val);
DUMP_HEX("EntryHi.ASID", (val & 0xff));
DUMP_CP0("EPC", read_c0_epc(), val);
DUMP_CP0("Status", read_c0_status(), val);
DUMP_CP0("Cause", read_c0_cause(), val);
DUMP_CP0("PRId", read_c0_prid(), val);
DUMP_CP0("HWREna", read_c0_hwrena(), val);
DUMP_CP0("Config", read_c0_config(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config1", read_c0_config1(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config2", read_c0_config2(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config3", read_c0_config3(), val);
if (val & MIPS_CONF3_ULRI)
DUMP_CP0("UserLocal", read_c0_userlocal(), val);
}
}
}
if (cpu_has_vz)
DUMP_CP0("GuestCtl0", read_c0_guestctl0(), val);
if (cpu_has_guestctl0ext)
DUMP_CP0("GuestCtl0Ext", read_c0_guestctl0ext(), val);
if (cpu_has_vz)
DUMP_CP0("GTOffset", read_c0_gtoffset(), val);
if (cpu_has_guestctl1) {
DUMP_CP0("GuestCtl1", read_c0_guestctl1(), val);
DUMP_HEX("GuestCtl1.ID", (val & GUESTCTL1_ID));
}
if (cpu_has_guestctl2) {
DUMP_CP0("GuestCtl2", read_c0_guestctl2(), val);
DUMP_HEX("GuestCtl2.VIP", (val & GUESTCTL2_VIP));
}
}
void __init plat_prepare_cpus(unsigned int max_cpus)
{
if (read_c0_config3() & (1<<2))
mipsmt_prepare_cpus();
}
void plat_smp_setup(void)
{
if (read_c0_config3() & (1<<2))
mipsmt_build_cpu_map(0);
}
static void __init msp_smtc_smp_setup(void)
{
if (read_c0_config3() & (1 << 2))
smp_num_siblings = smtc_build_cpu_map(0);
}
static int show_cpuinfo(struct seq_file *m, void *v)
{
struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
unsigned long n = (unsigned long) v - 1;
unsigned int version = cpu_data[n].processor_id;
unsigned int fp_vers = cpu_data[n].fpu_id;
char fmt [64];
int i;
#ifdef CONFIG_SMP
if (!cpu_online(n))
return 0;
#endif
/*
* For the first processor also print the system type
*/
if (n == 0) {
seq_printf(m, "system type\t\t: %s\n", get_system_type());
if (mips_get_machine_name())
seq_printf(m, "machine\t\t\t: %s\n",
mips_get_machine_name());
}
seq_printf(m, "processor\t\t: %ld\n", n);
sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
seq_printf(m, fmt, __cpu_name[n],
(version >> 4) & 0x0f, version & 0x0f,
(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
cpu_data[n].udelay_val / (500000/HZ),
(cpu_data[n].udelay_val / (5000/HZ)) % 100);
seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
seq_printf(m, "microsecond timers\t: %s\n",
cpu_has_counter ? "yes" : "no");
seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
seq_printf(m, "extra interrupt vector\t: %s\n",
cpu_has_divec ? "yes" : "no");
seq_printf(m, "hardware watchpoint\t: %s",
cpu_has_watch ? "yes, " : "no\n");
if (cpu_has_watch) {
seq_printf(m, "count: %d, address/irw mask: [",
cpu_data[n].watch_reg_count);
for (i = 0; i < cpu_data[n].watch_reg_count; i++)
seq_printf(m, "%s0x%04x", i ? ", " : "" ,
cpu_data[n].watch_reg_masks[i]);
seq_printf(m, "]\n");
}
seq_printf(m, "isa\t\t\t: mips1");
if (cpu_has_mips_2)
seq_printf(m, "%s", " mips2");
if (cpu_has_mips_3)
seq_printf(m, "%s", " mips3");
if (cpu_has_mips_4)
seq_printf(m, "%s", " mips4");
if (cpu_has_mips_5)
seq_printf(m, "%s", " mips5");
if (cpu_has_mips32r1)
seq_printf(m, "%s", " mips32r1");
if (cpu_has_mips32r2)
seq_printf(m, "%s", " mips32r2");
if (cpu_has_mips64r1)
seq_printf(m, "%s", " mips64r1");
if (cpu_has_mips64r2)
seq_printf(m, "%s", " mips64r2");
seq_printf(m, "\n");
seq_printf(m, "ASEs implemented\t:");
if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
if (cpu_has_vz) seq_printf(m, "%s", " vz");
if (cpu_has_msa) seq_printf(m, "%s", " msa");
if (cpu_has_eva) seq_printf(m, "%s", " eva");
seq_printf(m, "\n");
if (cpu_has_mmips) {
seq_printf(m, "micromips kernel\t: %s\n",
(read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no");
}
seq_printf(m, "shadow register sets\t: %d\n",
cpu_data[n].srsets);
seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask));
seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available");
seq_printf(m, fmt, 'D', vced_count);
seq_printf(m, fmt, 'I', vcei_count);
proc_cpuinfo_notifier_args.m = m;
proc_cpuinfo_notifier_args.n = n;
raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
&proc_cpuinfo_notifier_args);
seq_printf(m, "\n");
return 0;
}
static void __init ssmtc_smp_setup(void)
{
if (read_c0_config3() & (1 << 2))
mipsmt_build_cpu_map(0);
}
