static void start_timer(int timer, u64 interval)
{
union cvmx_ciu_timx timx;
unsigned long flags;
timx.u64 = 0;
timx.s.one_shot = 1;
timx.s.len = interval;
raw_local_irq_save(flags);
li.timer_start1 = read_c0_cvmcount();
cvmx_write_csr(CVMX_CIU_TIMX(timer), timx.u64);
/* Read it back to force wait until register is written. */
timx.u64 = cvmx_read_csr(CVMX_CIU_TIMX(timer));
li.timer_start2 = read_c0_cvmcount();
raw_local_irq_restore(flags);
}
static irqreturn_t cvm_oct_ciu_timer_interrupt(int cpl, void *dev_id)
{
u64 last_latency;
u64 last_int_cnt;
if (reset_stats) {
init_latency_info(&li, 0);
reset_stats = false;
} else {
last_int_cnt = read_c0_cvmcount();
last_latency = last_int_cnt - (li.timer_start1 + li.cpu_interval);
li.interrupt_cnt++;
li.latency_sum += last_latency;
if (last_latency > li.max_latency)
li.max_latency = last_latency;
if (last_latency < li.min_latency)
li.min_latency = last_latency;
}
start_timer(TIMER_NUM, li.io_interval);
return IRQ_HANDLED;
}
/*
* Low level initialize the Octeon PCI controller
*/
static void octeon_pci_initialize(void)
{
union cvmx_pci_cfg01 cfg01;
union cvmx_npi_ctl_status ctl_status;
union cvmx_pci_ctl_status_2 ctl_status_2;
union cvmx_pci_cfg19 cfg19;
union cvmx_pci_cfg16 cfg16;
union cvmx_pci_cfg22 cfg22;
union cvmx_pci_cfg56 cfg56;
/* Reset the PCI Bus */
cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
cvmx_read_csr(CVMX_CIU_SOFT_PRST);
udelay(2000); /* Hold PCI reset for 2 ms */
ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
ctl_status.s.max_word = 1;
ctl_status.s.timer = 1;
cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
/* Deassert PCI reset and advertize PCX Host Mode Device Capability
(64b) */
cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
cvmx_read_csr(CVMX_CIU_SOFT_PRST);
udelay(2000); /* Wait 2 ms after deasserting PCI reset */
ctl_status_2.u32 = 0;
ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
before any PCI reads. */
ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
ctl_status_2.s.bar2_enb = 1;
ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
ctl_status_2.s.bar2_esx = 1;
ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
/* BAR1 hole */
ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
ctl_status_2.s.bb1 = 1; /* BAR1 is big */
ctl_status_2.s.bb0 = 1; /* BAR0 is big */
}
octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
udelay(2000); /* Wait 2 ms before doing PCI reads */
ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
pr_notice("PCI Status: %s %s-bit\n",
ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
ctl_status_2.s.ap_64ad ? "64" : "32");
if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
union cvmx_pci_cnt_reg cnt_reg_start;
union cvmx_pci_cnt_reg cnt_reg_end;
unsigned long cycles, pci_clock;
cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
cycles = read_c0_cvmcount();
udelay(1000);
cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
cycles = read_c0_cvmcount() - cycles;
pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
(cycles / (mips_hpt_frequency / 1000000));
pr_notice("PCI Clock: %lu MHz\n", pci_clock);
}
/*
* TDOMC must be set to one in PCI mode. TDOMC should be set to 4
* in PCI-X mode to allow four outstanding splits. Otherwise,
* should not change from its reset value. Don't write PCI_CFG19
* in PCI mode (0x82000001 reset value), write it to 0x82000004
* after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
* MRBCM -> must be one.
*/
if (ctl_status_2.s.ap_pcix) {
cfg19.u32 = 0;
/*
* Target Delayed/Split request outstanding maximum
* count. [1..31] and 0=32. NOTE: If the user
* programs these bits beyond the Designed Maximum
* outstanding count, then the designed maximum table
* depth will be used instead. No additional
* Deferred/Split transactions will be accepted if
* this outstanding maximum count is
* reached. Furthermore, no additional deferred/split
* transactions will be accepted if the I/O delay/ I/O
* Split Request outstanding maximum is reached.
*/
cfg19.s.tdomc = 4;
/*
* Master Deferred Read Request Outstanding Max Count
* (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
* cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
* 5 2 110 6 3 111 7 3 For example, if these bits are
* programmed to 100, the core can support 2 DAC
* cycles, 4 SAC cycles or a combination of 1 DAC and
* 2 SAC cycles. NOTE: For the PCI-X maximum
* outstanding split transactions, refer to
* CRE0[22:20].
*/
cfg19.s.mdrrmc = 2;
/*
* Master Request (Memory Read) Byte Count/Byte Enable
* select. 0 = Byte Enables valid. In PCI mode, a
* burst transaction cannot be performed using Memory
* Read command=4?h6. 1 = DWORD Byte Count valid
* (default). In PCI Mode, the memory read byte
* enables are automatically generated by the
* core. Note: N3 Master Request transaction sizes are
* always determined through the
* am_attr[<35:32>|<7:0>] field.
*/
cfg19.s.mrbcm = 1;
octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
}
cfg01.u32 = 0;
cfg01.s.msae = 1; /* Memory Space Access Enable */
cfg01.s.me = 1; /* Master Enable */
cfg01.s.pee = 1; /* PERR# Enable */
cfg01.s.see = 1; /* System Error Enable */
cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */
octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
#ifdef USE_OCTEON_INTERNAL_ARBITER
/*
* When OCTEON is a PCI host, most systems will use OCTEON's
* internal arbiter, so must enable it before any PCI/PCI-X
* traffic can occur.
*/
{
union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
pci_int_arb_cfg.u64 = 0;
pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
}
#endif /* USE_OCTEON_INTERNAL_ARBITER */
/*
* Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
* TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
* 1..7.
*/
cfg16.u32 = 0;
cfg16.s.mltd = 1; /* Master Latency Timer Disable */
octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
/*
* Should be written to 0x4ff00. MTTV -> must be zero.
* FLUSH -> must be 1. MRV -> should be 0xFF.
*/
cfg22.u32 = 0;
/* Master Retry Value [1..255] and 0=infinite */
cfg22.s.mrv = 0xff;
/*
* AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
* N3K operation.
*/
cfg22.s.flush = 1;
octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
/*
* MOST Indicates the maximum number of outstanding splits (in -1
* notation) when OCTEON is in PCI-X mode. PCI-X performance is
* affected by the MOST selection. Should generally be written
* with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
* depending on the desired MOST of 3, 2, 1, or 0, respectively.
*/
cfg56.u32 = 0;
cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */
cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */
cfg56.s.roe = 1; /* Relaxed Ordering Enable */
cfg56.s.mmbc = 1; /* Maximum Memory Byte Count
[0=512B,1=1024B,2=2048B,3=4096B] */
cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1
.. 7=32] */
octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
/*
* Affects PCI performance when OCTEON services reads to its
* BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
* 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
* PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
* these values need to be changed so they won't possibly prefetch off
* of the end of memory if PCI is DMAing a buffer at the end of
* memory. Note that these values differ from their reset values.
*/
octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
}
