void ddramc_print_config_regs(unsigned int base_address)
{
dbg_very_loud("\n\nMPDDR Controller Registers configurations:\n");
dbg_very_loud("MPDDRC_MDR: %d\n",
read_ddramc(base_address, HDDRSDRC2_MDR));
dbg_very_loud("MPDDRC_READ_DATA_PATH: %d\n",
read_ddramc(base_address, MPDDRC_RD_DATA_PATH));
dbg_very_loud("MPDDRC_IO_CALIBR: %d\n",
read_ddramc(base_address, MPDDRC_IO_CALIBR));
dbg_very_loud("MPDDRC_TPR0: %d\n",
read_ddramc(base_address, HDDRSDRC2_T0PR));
dbg_very_loud("MPDDRC_TPR1: %d\n",
read_ddramc(base_address, HDDRSDRC2_T1PR));
dbg_very_loud("MPDDRC_TPR2: %d\n",
read_ddramc(base_address, HDDRSDRC2_T2PR));
dbg_very_loud("MPDDRC_RTR: %d\n",
read_ddramc(base_address, HDDRSDRC2_RTR));
dbg_very_loud("MPDDRC_CR: %d\n",
read_ddramc(base_address, HDDRSDRC2_CR));
}
int ddram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int ba_offset;
unsigned int cr = 0;
/* compute BA[] offset according to CR configuration */
ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
if (ddramc_decodtype_is_seq(ddramc_config->cr))
ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
dbg_log(3, " ba_offset = %x ...\n\r", ba_offset);
/*
* Step 1: Program the memory device type into the Memory Device Register
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program the feature of DDR2-SDRAM device into
* the Timing Register, and into the Configuration Register
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: An NOP command is issued to the DDR2-SDRAM
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* Now, clocks which drive the DDR2-SDRAM device are enabled */
/* A minimum pause wait 200 us is provided to precede any signal toggle.
(6 core cycles per iteration, core is at 396MHz: min 13340 loops) */
udelay(200);
/*
* Step 4: An NOP command is issued to the DDR2-SDRAM
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* Now, CKE is driven high */
/* wait 400 ns min */
udelay(1);
/*
* Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 6: An Extended Mode Register set(EMRS2) cycle is issued to chose between commercial or high
* temperature operations.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x2 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 7: An Extended Mode Register set(EMRS3) cycle is issued
* to set the Extended Mode Register to "0".
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x3 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 8: An Extened Mode Register set(EMRS1) cycle is issued to enable DLL,
* and to program D.I.C(Output Driver Impedance Control)
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/* An additional 200 cycles of clock are required for locking DLL */
udelay(1);
/*
* Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset)
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
/*
* Step 10: A Mode Register set(MRS) cycle is issied to reset DLL.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1:0] bits are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned int *)(ram_address + (0x0 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/* wait 400 ns min (not needed on certain DDR2 devices) */
udelay(1);
/*
* Step 12: Two auto-refresh (CBR) cycles are provided.
* Program the auto refresh command (CBR) into the Mode Register.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/* wait TRFC cycles min (135 ns min) extended to 400 ns */
udelay(1);
/* Set 2nd CBR */
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/* wait TRFC cycles min (135 ns min) extended to 400 ns */
udelay(1);
/*
* Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_DLL_RESET_ENABLED));
/*
* Step 14: A Mode Register set (MRS) cycle is issued to program
* the parameters of the DDR2-SDRAM devices, in particular CAS latency,
* burst length and to disable DDL reset.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1:0] bits are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned int *)(ram_address + (0x0 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 15: Program OCD field into the Configuration Register
* to high (OCD calibration default).
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_OCD_DEFAULT);
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 17: Program OCD field into the Configuration Register
* to low (OCD calibration mode exit).
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_OCD_DEFAULT));
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.
* Perform a write access to DDR2-SDRAM to acknowledge this command.
* The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/* wait 2 cycles min (of tCK) = 15 ns min */
udelay(1);
/*
* Step 19: A Nornal mode command is provided.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*(((unsigned volatile int *)ram_address)) = 0;
/*
* Step 20: Perform a write access to any DDR2-SDRAM address
*/
*(((unsigned volatile int *)ram_address)) = 0;
/*
* Step 21: Write the refresh rate into the count field in the Refresh Timer register.
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
/*
* Now we are ready to work on the DDRSDR
* wait for end of calibration
*/
udelay(10);
return 0;
}
int ddr3_sdram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int ba_offset;
/* Compute BA[] offset according to CR configuration */
ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
if (!(ddramc_config->cr & AT91C_DDRC2_DECOD_INTERLEAVED))
ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
dbg_very_loud(" ba_offset = %x ...\n", ba_offset);
/*
* Step 1: Program the memory device type in the MPDDRC Memory Device Register
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program features of the DDR3-SDRAM device in the MPDDRC
* Configuration Register and in the MPDDRC Timing Parameter 0 Register
* /MPDDRC Timing Parameter 1 Register
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: A NOP command is issued to the DDR3-SRAM.
* Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR).
* The application must write a one to the MODE field in the MPDDRC_MR
* Perform a write access to any DDR3-SDRAM address to acknowledge this command.
* The clock which drive the DDR3-SDRAM device are now enabled.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 4: A pause of at least 500us must be observed before a single toggle.
*/
udelay(500);
/*
* Step 5: A NOP command is issued to the DDR3-SDRAM
* Program the NOP command in the MPDDRC_MR.
* The application must write a one to the MODE field in the MPDDRC_MR.
* Perform a write access to any DDR3-SDRAM address to acknowledge this command.
* CKE is now driven high.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 6: An Extended Mode Register Set (EMRS2) cycle is issued to choose
* between commercial or high temperature operations. The application must
* write a five to the MODE field in the MPDDRC_MR and perform a write
* access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signal BA[2] is set to 0,
* BA[1] is set to 1 and signal BA[0] is set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x2 << ba_offset))) = 0;
/*
* Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
* the Extended Mode Register to 0. The application must write a five
* to the MODE field in the MPDDRC_MR and perform a write access to the
* DDR3-SDRAM to acknowledge this command. The write address must be
* chosen so that signal BA[2] is set to 0, BA[1] is set to 1 and signal
* BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x3 << ba_offset))) = 0;
/*
* Step 8: An Extended Mode Register Set (EMRS1) cycle is issued to
* disable and to program O.D.S. (Output Driver Strength).
* The application must write a five to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signal BA[2:1] is set to 0
* and signal BA[0] is set to 1.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);
*((unsigned int *)(ram_address + (0x1 << ba_offset))) = 0;
/*
* Step 9: Write a one to the DLL bit (enable DLL reset) in the MPDDRC
* Configuration Register (MPDDRC_CR)
*/
#if 0
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
#endif
/*
* Step 10: A Mode Register Set (MRS) cycle is issued to reset DLL.
* The application must write a three to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signals BA[2:0] are set to 0
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD);
*((unsigned int *)ram_address) = 0;
udelay(50);
/*
* Step 11: A Calibration command (MRS) is issued to calibrate RTT and
* RON values for the Process Voltage Temperature (PVT).
* The application must write a six to the MODE field in the MPDDRC_MR
* and perform a write access to the DDR3-SDRAM to acknowledge this command.
* The write address must be chosen so that signals BA[2:0] are set to 0.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_DEEP_CMD);
*((unsigned int *)ram_address) = 0;
/*
* Step 12: A Normal Mode command is provided.
* Program the Normal mode in the MPDDRC_MR and perform a write access
* to any DDR3-SDRAM address to acknowledge this command.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*((unsigned int *)ram_address) = 0;
/*
* Step 13: Perform a write access to any DDR3-SDRAM address.
*/
*((unsigned int *)ram_address) = 0;
/*
* Step 14: Write the refresh rate into the COUNT field in the MPDDRC
* Refresh Timer Register (MPDDRC_RTR):
* refresh rate = delay between refresh cycles.
* The DDR3-SDRAM device requires a refresh every 7.81 us.
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
return 0;
}
int lpddr2_sdram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int cr;
write_ddramc(base_address, MPDDRC_LPDDR2_LPR,
ddramc_config->lpddr2_lpr);
/*
* Step 1: Program the memory device type into
* the Memory Device Register
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program the feature of Low-power DDR2-SDRAM device into
* the Timing Register, and into the Configuration Register
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: An NOP command is issued to the Low-power DDR2-SDRAM
* Program the NOP command into the Mode Register, the application must
* set the MODE field to 1 in the Mode Register. Perform a write access
* to any Low-power DDR2-SDRAM address to acknowledge this command.
* Now, clocks which drive Low-power DDR2-SDRAM device is enabled.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* A minimum pause of 100 ns must be reserved
* to precede any single toggle
*/
udelay(1);
/*
* Step 4: An NOP command is issued to the Low-power DDR2-SDRAM.
* Now, CKE is drive high.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* A minimum pause of 200us must be satisfied before Reset Command*/
udelay(200);
/*
* Step 5: A reset command is issued to the Low-power DDR2-SDRAM.
* Now, the reset command is issued.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(63) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* A minimum pause of 1 us must be satisfied befor any commands */
udelay(1);
/*
* Step 6: A Mode Register Read command is issued to the Low-power
* DDR2-SDRAM. Now, the Mode Register Read command is issued.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(0) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/* A minimum pause of 10 us must be satified before any commands */
udelay(10);
/*
* Step 7: a calibration command is issued to the Low-power DDR2-SDRAM.
* Now, the ZQ Calibration command is issued.
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
cr &= ~AT91C_DDRC2_ZQ;
cr |= AT91C_DDRC2_ZQ_RESET;
write_ddramc(base_address, HDDRSDRC2_CR, cr);
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(10) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
udelay(1);
cr = read_ddramc(base_address, HDDRSDRC2_CR);
cr &= ~AT91C_DDRC2_ZQ;
cr |= AT91C_DDRC2_ZQ_SHORT;
write_ddramc(base_address, HDDRSDRC2_CR, cr);
/*
* Step 8: A Mode Register Write command is issued to the Low-power
* DDR2-SDRAM. Now, the Mode Register Write command is issued.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(1) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
udelay(1);
/*
* Step 9: A Mode Register Write command is issued to the Low-power
* DDR2-SDRAM. Now, the Mode Register Write command is issued.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(2) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
udelay(1);
/*
* Step 10: A Mode Register Write command is issued to the Low-power
* DDR2-SDRAM. Now, the Mode Register Write command is issued.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(3) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
udelay(1);
/*
* Step 11: A Mode Register Write command is issued to the Low-power
* DDR2-SDRAM. Now, the Mode Register Write command is issued.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(16) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
udelay(1);
/*
* Step 12: Write the refresh rate into the COUNT field in
* the Refresh Timer register.
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*((unsigned volatile int *)ram_address) = 0;
udelay(1);
/* Launch short ZQ calibration */
cr = read_ddramc(base_address, HDDRSDRC2_CR);
cr &= ~AT91C_DDRC2_ZQ;
cr |= AT91C_DDRC2_ZQ_SHORT;
write_ddramc(base_address, HDDRSDRC2_CR, cr);
*((unsigned volatile int *)ram_address) = 0;
write_ddramc(base_address, MPDDRC_LPDDR2_TIM_CAL,
ddramc_config->tim_calr);
return 0;
}
int ddr3_init(const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value)
{
struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
u32 ba_off;
/* Compute bank offset according to NC in configuration register */
ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
if (ddr2_decodtype_is_seq(mpddr_value->cr))
ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
/* Program the memory device type */
writel(mpddr_value->md, &mpddr->md);
/*
* Program features of the DDR3-SDRAM device and timing parameters
*/
writel(mpddr_value->cr, &mpddr->cr);
writel(mpddr_value->tpr0, &mpddr->tpr0);
writel(mpddr_value->tpr1, &mpddr->tpr1);
writel(mpddr_value->tpr2, &mpddr->tpr2);
/* A NOP command is issued to the DDR3-SRAM */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
/* A pause of at least 500us must be observed before a single toggle. */
udelay(500);
/* A NOP command is issued to the DDR3-SDRAM */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
/*
* An Extended Mode Register Set (EMRS2) cycle is issued to choose
* between commercial or high temperature operations.
*/
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x2 << ba_off));
/*
* Step 7: An Extended Mode Register Set (EMRS3) cycle is issued to set
* the Extended Mode Register to 0.
*/
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x3 << ba_off));
/*
* An Extended Mode Register Set (EMRS1) cycle is issued to disable and
* to program O.D.S. (Output Driver Strength).
*/
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
ram_address + (0x1 << ba_off));
#if 0
/*
* Write a one to the DLL bit (enable DLL reset) in the MPDDRC
* Configuration Register.
*/
cr = read_ddramc(base_address, HDDRSDRC2_CR);
write_ddramc(base_address, HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED);
#endif
/* A Mode Register Set (MRS) cycle is issued to reset DLL. */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
udelay(50);
/*
* A Calibration command (MRS) is issued to calibrate RTT and RON
* values for the Process Voltage Temperature (PVT).
*/
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_DEEP_CMD, ram_address);
/* A Normal Mode command is provided. */
atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
/* Perform a write access to any DDR3-SDRAM address. */
writel(0, ram_address);
/*
* Write the refresh rate into the COUNT field in the MPDDRC
* Refresh Timer Register (MPDDRC_RTR):
*/
writel(mpddr_value->rtr, &mpddr->rtr);
return 0;
}
int lpddr3_sdram_initialize(unsigned int base_address,
unsigned int ram_address,
struct ddramc_register *ddramc_config)
{
unsigned int reg;
write_ddramc(base_address, MPDDRC_LPDDR2_LPR,
ddramc_config->lpddr2_lpr);
/*
* Step 1: Program the memory device type in the MPDDRC Memory
* Device Register.
*/
write_ddramc(base_address, HDDRSDRC2_MDR, ddramc_config->mdr);
/*
* Step 2: Program features of the low-power DDR3-SDRAM device
* in the MPDDRC Configuration Register and in the MPDDRC Timing
* Parameter 0 Register/MPDDRC Timing Parameter 1 Register.
*/
write_ddramc(base_address, HDDRSDRC2_CR, ddramc_config->cr);
write_ddramc(base_address, HDDRSDRC2_T0PR, ddramc_config->t0pr);
write_ddramc(base_address, HDDRSDRC2_T1PR, ddramc_config->t1pr);
write_ddramc(base_address, HDDRSDRC2_T2PR, ddramc_config->t2pr);
/*
* Step 3: A NOP command is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 4: A pause of at least 100ns must be observed before
* a single toggle.
*/
udelay(1);
/*
* Step 5: A NOP command is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 6: A pause of at least 200us must be observed before issuing
* a Reset Command
*/
udelay(200);
/*
* Step 7: A Reset command is issued to the Low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(63) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 8: A pause of at least tINIT5 must be observed before issuing
* any commands.
*/
udelay(1);
/*
* Step 9: A Calibration command is issued to the low-power DDR3-SDRAM.
*/
reg = read_ddramc(base_address, HDDRSDRC2_CR);
reg &= ~AT91C_DDRC2_ZQ;
reg |= AT91C_DDRC2_ZQ_RESET;
write_ddramc(base_address, HDDRSDRC2_CR, reg);
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(10) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
reg = read_ddramc(base_address, HDDRSDRC2_CR);
reg &= ~AT91C_DDRC2_ZQ;
reg |= AT91C_DDRC2_ZQ_SHORT;
write_ddramc(base_address, HDDRSDRC2_CR, reg);
/*
* Step 10: A Mode Register Write command with 1 to the MRS field
* is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(1) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 11: A Mode Register Write command with 2 to the MRS field
* is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(2) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 12: A Mode Register Write command with 3 to the MRS field
* is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(3) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 13: A Mode Register Write command with 16 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(16) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 14: In the DDR Configuration Register, open the input buffers.
*/
reg = readl(AT91C_BASE_SFR + SFR_DDRCFG);
reg |= AT91C_DDRCFG_FDQIEN;
reg |= AT91C_DDRCFG_FDQSIEN;
writel(reg, AT91C_BASE_SFR + SFR_DDRCFG);
/*
* Step 15: A NOP command is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 16: A Mode Register Read command with 5 to the MRS field
* is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(5) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 17: A Mode Register Read command with 6 to the MRS field
* is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(6) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 18: A Mode Register Read command with 8 to the MRS field
* is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(8) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 19: A Mode Register Read command with 0 to the MRS field
* is issued to the low-power DDR3-SDRAM.
*/
write_ddramc(base_address, HDDRSDRC2_MR,
AT91C_DDRC2_MRS(0) | AT91C_DDRC2_MODE_LPDDR2_CMD);
*((unsigned volatile int *)ram_address) = 0;
/*
* Step 20: A Normal Mode command is provided.
*/
write_ddramc(base_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD);
*((unsigned int *)ram_address) = 0;
/*
* Step 21: In the DDR Configuration Register, close the input buffers.
*/
reg = readl(AT91C_BASE_SFR + SFR_DDRCFG);
reg &= ~AT91C_DDRCFG_FDQIEN;
reg &= ~AT91C_DDRCFG_FDQSIEN;
writel(reg, AT91C_BASE_SFR + SFR_DDRCFG);
/*
* Step 22: Write the refresh rate into the COUNT field in the MPDDRC
* Refresh Timer Register. The low-power DDR3-SDRAM device requires
* a refresh every 3.9 us.
*/
write_ddramc(base_address, HDDRSDRC2_RTR, ddramc_config->rtr);
return 0;
}