static int cpc_read(struct cpc_reg *reg, u64 *val) { int ret_val = 0; *val = 0; if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { void __iomem *vaddr = GET_PCC_VADDR(reg->address); switch (reg->bit_width) { case 8: *val = readb_relaxed(vaddr); break; case 16: *val = readw_relaxed(vaddr); break; case 32: *val = readl_relaxed(vaddr); break; case 64: *val = readq_relaxed(vaddr); break; default: pr_debug("Error: Cannot read %u bit width from PCC\n", reg->bit_width); ret_val = -EFAULT; } } else ret_val = acpi_os_read_memory((acpi_physical_address)reg->address, val, reg->bit_width); return ret_val; }
void xcv_setup_link(bool link_up, int link_speed) { u64 cfg; int speed = 2; if (!xcv) { dev_err(&xcv->pdev->dev, "XCV init not done, probe may have failed\n"); return; } if (link_speed == 100) speed = 1; else if (link_speed == 10) speed = 0; if (link_up) { /* set operating speed */ cfg = readq_relaxed(xcv->reg_base + XCV_CTL); cfg &= ~0x03; cfg |= speed; writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); /* Reset datapaths */ cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg |= TX_DATA_RESET | RX_DATA_RESET; writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); /* Enable the packet flow */ cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg |= TX_PKT_RESET | RX_PKT_RESET; writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); /* Return credits to RGX */ writeq_relaxed(0x01, xcv->reg_base + XCV_BATCH_CRD_RET); } else { /* Disable packet flow */ cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg &= ~(TX_PKT_RESET | RX_PKT_RESET); writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); readq_relaxed(xcv->reg_base + XCV_RESET); } }
static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) { int ret_val = 0; void __iomem *vaddr = 0; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cpc_reg *reg = ®_res->cpc_entry.reg; if (reg_res->type == ACPI_TYPE_INTEGER) { *val = reg_res->cpc_entry.int_value; return ret_val; } *val = 0; if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) vaddr = reg_res->sys_mem_vaddr; else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) return cpc_read_ffh(cpu, reg, val); else return acpi_os_read_memory((acpi_physical_address)reg->address, val, reg->bit_width); switch (reg->bit_width) { case 8: *val = readb_relaxed(vaddr); break; case 16: *val = readw_relaxed(vaddr); break; case 32: *val = readl_relaxed(vaddr); break; case 64: *val = readq_relaxed(vaddr); break; default: pr_debug("Error: Cannot read %u bit width from PCC\n", reg->bit_width); ret_val = -EFAULT; } return ret_val; }
void xcv_init_hw(void) { u64 cfg; /* Take DLL out of reset */ cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg &= ~DLL_RESET; writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); /* Take clock tree out of reset */ cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg &= ~CLK_RESET; writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); /* Wait for DLL to lock */ msleep(1); /* Configure DLL - enable or bypass * TX no bypass, RX bypass */ cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); cfg &= ~0xFF03; cfg |= CLKRX_BYP; writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); /* Enable compensation controller and force the * write to be visible to HW by readig back. */ cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg |= COMP_EN; writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); readq_relaxed(xcv->reg_base + XCV_RESET); /* Wait for compensation state machine to lock */ msleep(10); /* enable the XCV block */ cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg |= PORT_EN; writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); cfg = readq_relaxed(xcv->reg_base + XCV_RESET); cfg |= CLK_RESET; writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); }
static u64 nic_reg_read(struct nicpf *nic, u64 offset) { return readq_relaxed(nic->reg_base + offset); }