void set_current_gate(void)
{
unsigned long value, gate;
//change to mode0
value = regRead32(POWER_MODE_CTRL);
value = FIELD_SET(value, POWER_MODE_CTRL, MODE, MODE0);
regWrite32(POWER_MODE_CTRL, value);
// Don't forget to set up power mode0 gate properly.
gate = regRead32(CURRENT_POWER_GATE);
gate = FIELD_SET(gate, CURRENT_POWER_GATE, 2D, ENABLE);
regWrite32(POWER_MODE0_GATE, gate);
}
// Program new power mode.
void setPower(unsigned long nGates, unsigned long Clock)
{
unsigned long gate_reg, clock_reg;
unsigned long control_value;
// Get current power mode.
control_value = FIELD_GET(regRead32(POWER_MODE_CTRL),
POWER_MODE_CTRL,
MODE);
switch (control_value)
{
case POWER_MODE_CTRL_MODE_MODE0:
// Switch from mode 0 to mode 1.
gate_reg = POWER_MODE1_GATE;
clock_reg = POWER_MODE1_CLOCK;
control_value = FIELD_SET(control_value,
POWER_MODE_CTRL, MODE, MODE1);
break;
case POWER_MODE_CTRL_MODE_MODE1:
case POWER_MODE_CTRL_MODE_SLEEP:
// Switch from mode 1 or sleep to mode 0.
gate_reg = POWER_MODE0_GATE;
clock_reg = POWER_MODE0_CLOCK;
control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE0);
break;
default:
// Invalid mode
return;
}
// Program new power mode.
regWrite32(gate_reg, nGates);
regWrite32(clock_reg, Clock);
regWrite32(POWER_MODE_CTRL, control_value);
// When returning from sleep, wait until finished.
while (FIELD_GET(regRead32(POWER_MODE_CTRL),
POWER_MODE_CTRL,
SLEEP_STATUS) == POWER_MODE_CTRL_SLEEP_STATUS_ACTIVE) ;
}
static void tc3162_pcie_fixup_ra63165(struct pci_dev *dev)
{
uint32 tmp;
#if defined(CONFIG_TCSUPPORT_BONDING)
int i;
#endif
/* setup COMMAND register */
pci_write_config_word(dev, PCI_COMMAND,
(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
#if defined(CONFIG_TCSUPPORT_BONDING)
//Enable slave RC ECRC count . //bus1, dev1
regWrite32(0xbfb80020, 0x1080118);
tmp = regRead32(0xbfb80024);
regWrite32(0xbfb80024, (tmp | (1<<8)));
//config PCIe RC/EP VC mapping
//set bus0, dev0, fun0, reg154 (setup VC0)
regWrite32(0xbfb80020, 0x154);
regWrite32(0xbfb80024, 0X80000001);
//set bus0, dev0, fun0, reg160 (setup VC1)
regWrite32(0xbfb80020, 0x160);
regWrite32(0xbfb80024, 0X81000002);
//set bus1, dev0, fun0, reg154 (setup VC0)
regWrite32(0xbfb80020, 0x1000154);
regWrite32(0xbfb80024, 0X80000001);
//set bus1, dev0, fun0, reg160 (setup VC1)
regWrite32(0xbfb80020, 0x1000160);
regWrite32(0xbfb80024, 0X81000002);
//config slave chip EP MSI
regWrite32(0xbfb80020, 0x1000050);
tmp = regRead32(0xbfb80024);
regWrite32(0xbfb80020, 0x1000050);
regWrite32(0xbfb80024, (tmp | 0x510000));
regWrite32(0xbfb80020, 0x1000054);
regWrite32(0xbfb80024, 0x20af1000);
regWrite32(0xbfb80020, 0x100005c);
regWrite32(0xbfb80024, 0x0);
//setup RC0 MSI address reg
regWrite32(0xbfb82090, 0x20af1000);
//setup RC0 Pbus/Rbus VC mapping
regWrite32(0xbfb82094, 0x1);
regWrite32(0xbfb83094, 0x0);
//wait RC0 VC1 set up OK
for(i=0 ; i<1000 ; i++){
mdelay(1);
regWrite32(0xbfb80020, 0x164);
if((regRead32(0xbfb80024) & (1<<17)) == 0){
break;
}
}
#endif
//pci-e interrupt enable_dma
if(isRT63365 || isMT751020){
#if defined(CONFIG_TCSUPPORT_BONDING)
if((regRead32(0xbfb82050) & 0x1) != 0){
/* slave dmt */
tmp = regRead32(0xbfb8000c);
regWrite32(0xbfb8000c, (tmp | (1<<23)));
/* slave gdma */
tmp = regRead32(0xbfb8000c);
regWrite32(0xbfb8000c, (tmp | (1<<25)));
if(regRead32(0xbfb80050) == 1){
/* wifi 0 (slave)*/
tmp = regRead32(0xbfb8000c);
regWrite32(0xbfb8000c, (tmp | (1<<22)));
}
}
#else
if((regRead32(0xbfb82050) & 0x1) != 0){
tmp = regRead32(0xbfb8000c);
regWrite32(0xbfb8000c, (tmp | (1<<20)));
}
#endif
//second band
if(dual_band_support){
if((regRead32(0xbfb83050) & 0x1) != 0){
if(isMT751020){
tmp = regRead32(0xbfb8000c);
regWrite32(0xbfb8000c, (tmp | (1<<26)));
}else{
tmp = regRead32(0xbfb8000c);
regWrite32(0xbfb8000c, (tmp | (1<<21)));
}
}
}
}else{
tmp = regRead32(0xbfb8100c);
regWrite32(0xbfb8100c, (tmp | (1<<20)));
}
if(isMT751020){
pcie_timeout_disable();
aer_config(1);
}
}
