static int _send(netdev2_t *netdev, const struct iovec *vector, int count) {
encx24j600_t * dev = (encx24j600_t *) netdev;
lock(dev);
/* wait until previous packet has been sent */
while ((reg_get(dev, ECON1) & TXRTS));
/* copy packet to SRAM */
size_t len = 0;
for (int i = 0; i < count; i++) {
sram_op(dev, WGPDATA, (i ? 0xFFFF : TX_BUFFER_START), vector[i].iov_base, vector[i].iov_len);
len += vector[i].iov_len;
}
/* set start of TX packet and length */
reg_set(dev, ETXST, TX_BUFFER_START);
reg_set(dev, ETXLEN, len);
/* initiate sending */
cmd(dev, SETTXRTS);
/* wait for sending to complete */
/* (not sure if it is needed, keeping the line uncommented) */
/*while ((reg_get(dev, ECON1) & TXRTS));*/
unlock(dev);
return len;
}
int main(void)
{
hw_init();
while(1)
{
/* Set LED on */
reg_wr((u32)GPIOI_BSRR, (0x1 << 1) );
/* Start Timer2 */
reg_set(TIM2_CR1, 1);
/* Wait Timer2 ends */
while(reg_rd(TIM2_CR1) & 1)
;
/* Set LED off */
reg_wr((u32)GPIOI_BSRR, (0x1 << 17) );
/* Start Timer2 */
reg_set(TIM2_CR1, 1);
/* Wait Timer2 ends */
while(reg_rd(TIM2_CR1) & 1)
;
}
}
static int _init(netdev2_t *encdev)
{
encx24j600_t *dev = (encx24j600_t *) encdev;
DEBUG("encx24j600: starting initialization...\n");
/* setup IO */
gpio_init(dev->cs, GPIO_OUT);
gpio_set(dev->cs);
gpio_init_int(dev->int_pin, GPIO_IN_PU, GPIO_FALLING, encx24j600_isr, (void*)dev);
if (spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, ENCX24J600_SPI_SPEED) < 0) {
return -1;
}
lock(dev);
/* initialization procedure as described in data sheet (39935c.pdf) */
do {
do {
xtimer_usleep(ENCX24J600_INIT_DELAY);
reg_set(dev, ENC_EUDAST, 0x1234);
xtimer_usleep(ENCX24J600_INIT_DELAY);
} while (reg_get(dev, ENC_EUDAST) != 0x1234);
while (!(reg_get(dev, ENC_ESTAT) & ENC_CLKRDY));
/* issue System Reset */
cmd(dev, ENC_SETETHRST);
/* make sure initialization finalizes */
xtimer_usleep(1000);
} while (!(reg_get(dev, ENC_EUDAST) == 0x0000));
/* configure flow control */
phy_reg_set(dev, ENC_PHANA, 0x05E1);
reg_set_bits(dev, ENC_ECON2, ENC_AUTOFC);
/* setup receive buffer */
reg_set(dev, ENC_ERXST, RX_BUFFER_START);
reg_set(dev, ENC_ERXTAIL, RX_BUFFER_END);
dev->rx_next_ptr = RX_BUFFER_START;
/* configure receive filter to receive multicast frames */
reg_set_bits(dev, ENC_ERXFCON, ENC_MCEN);
/* setup interrupts */
reg_set_bits(dev, ENC_EIE, ENC_PKTIE | ENC_LINKIE);
cmd(dev, ENC_ENABLERX);
cmd(dev, ENC_SETEIE);
DEBUG("encx24j600: initialization complete.\n");
unlock(dev);
#ifdef MODULE_NETSTATS_L2
memset(&netdev->stats, 0, sizeof(netstats_t));
#endif
return 0;
}
static int ioctl_set_opts(void *user_addr)
{
struct pme_ctrl_opts opts;
u32 val;
if (copy_from_user(&opts, user_addr, sizeof(opts)))
return -EFAULT;
/* Validation */
if (opts.flags & PME_CTRL_OPT_KVLTS)
if (opts.kvlts < 1 || opts.kvlts > 16)
return -EINVAL;
if (opts.flags & PME_CTRL_OPT_SWDB)
reg_set(regs, SWDB, opts.swdb);
if (opts.flags & PME_CTRL_OPT_EOSRP) {
val = reg_get(regs, SREC);
/* 18 lower bits */
val = (val & ~PME_DMA_EOSRP_MASK) |
(opts.eosrp & PME_DMA_EOSRP_MASK);
reg_set(regs, SREC, val);
}
if (opts.flags & PME_CTRL_OPT_DRCC)
reg_set(regs, DRCC, opts.drcc);
if (opts.flags & PME_CTRL_OPT_KVLTS) {
val = opts.kvlts - 1;
reg_set(regs, KVLTS, val);
}
if (opts.flags & PME_CTRL_OPT_MCL) {
val = reg_get(regs, KEC);
/* 15 lower bits */
val = (val & ~PME_DMA_MCL_MASK) |
(opts.mcl & PME_DMA_MCL_MASK);
reg_set(regs, KEC, val);
}
return 0;
};
static void hw_init_timer(void)
{
reg_set(RCC_APB1ENR, 0x01); /* Activate Timer2 */
/* Configure Timer2 */
reg_wr (TIM2_CR1, 0x0200); /* Input clock divided by 4 */
reg_wr (TIM2_ARR, 0x8000); /* Value used when reloaded */
reg_wr (TIM2_PSC, 0x80); /* Prescaler */
reg_set(TIM2_CR1, 0x08); /* Set OPM (one-pulse-mode) */
}
static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
{
if (on) {
reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
} else {
reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
}
}
/*
* Increases the value of a selected register by a constant
* des - destination register
* const8 - constant to add
*/
void
_inc (int des, int const8)
{
check (des, TYPE_DES, 1);
check (const8, TYPE_CONST8, 2);
/* Set des to des + const8 */
reg_set (0x1, des, mem.registers[des] + const8);
/* Set r1 */
reg_set (0x0, 0x1, ((mem.registers[des] > 127) ? 1 : -1));
}
static void test_regpush(void) {
reg_setSpecial(rS,STACK_ADDR);
reg_setSpecial(rO,STACK_ADDR);
// arrange things so that a push(255) needs to write a register to memory first
{
reg_set(254,0x1234);
reg_push(254);
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7F8);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7F8);
}
else {
ex_push(&env);
reg_push(255);
test_assertFalse(true);
}
ex_pop();
reg_pop(0);
}
// arrange things so that a push(0) sets $0, which needs to write a register to memory first
{
reg_set(254,0x1234);
reg_push(254);
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7F8);
jmp_buf env;
int ex = setjmp(env);
if(ex != EX_NONE) {
test_assertOcta(reg_getSpecial(rL),0);
test_assertOcta(reg_getSpecial(rS),STACK_ADDR);
test_assertOcta(reg_getSpecial(rO),STACK_ADDR + 0x7F8);
}
else {
ex_push(&env);
reg_push(0);
test_assertFalse(true);
}
ex_pop();
reg_pop(0);
}
}
/*
* Integer multiplication
* des - destination register
* src1 - factor
* src2 - factor
*/
void
_mul (int des, int src1, int src2)
{
check (des, TYPE_DES, 1);
check (src1, TYPE_SRC, 2);
check (src2, TYPE_SRC, 3);
/* Calculate and store/update r1 */
int prod = src1 * src2;
reg_set (0x1, des, prod);
reg_set (0x0, 0x1, prod);
}
static void hw_init_clock(void)
{
u32 val;
/* 1) Activate HSE, that will be used as PLL source */
/* Clear HSEON bit */
reg_clr(RCC_CR, 0x00010000);
/* Clear HSEBYP bit */
reg_clr(RCC_CR, 0x00040000);
/* Activate HSE (set HSEON) */
reg_set(RCC_CR, 0x00010000);
/* Wait until HSERDY bit set */
while( (reg_rd(RCC_CR) & 0x00020000) == 0)
;
/* 2) Configure and activate PLL */
/* Configure PLL */
val = (432 << 6); // set N (VCO multiplier)
val |= 25; // set M (VCO divisor)
val |= ( 0 << 16); // set P (output divisor
val |= ( 9 << 24); // set Q (peripheral divisor)
reg_wr(RCC_PLLCFGR, val);
/* Activate PLL */
reg_set(RCC_CR, 0x01000000);
while( (reg_rd(RCC_CR) & 0x02000000) == 0)
;
/* 3) Update flash latency, and peripheral bus prescaler */
/* Set Flash latency to 7 */
reg_set(FLASH_ACR, 0x07);
/* PCLK1 - Set APB1 clock divider to 4 (value 5) */
reg_set(RCC_CFGR, (5 << 10) );
/* PCLK2 - Set APB2 clock divider to 2 (value 4) */
reg_set(RCC_CFGR, (4 << 13) );
/* 4) Switch the current clock to PLL */
/* Change the clock source */
val = reg_rd(RCC_CFGR);
val &= ~0x03;
val |= 0x02;
reg_wr(RCC_CFGR, val);
/* Wait until, clock source is modified */
while( (reg_rd(RCC_CFGR) & 0x0C) != (0x02 << 2))
;
}
static int ak881x_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct ak881x *ak881x = to_ak881x(client);
u8 vp1;
if (std == V4L2_STD_NTSC_443) {
vp1 = 3;
ak881x->lines = 480;
} else if (std == V4L2_STD_PAL_M) {
vp1 = 5;
ak881x->lines = 480;
} else if (std == V4L2_STD_PAL_60) {
vp1 = 7;
ak881x->lines = 480;
} else if (std && !(std & ~V4L2_STD_PAL)) {
vp1 = 0xf;
ak881x->lines = 576;
} else if (std && !(std & ~V4L2_STD_NTSC)) {
vp1 = 0;
ak881x->lines = 480;
} else {
/* No SECAM or PAL_N/Nc supported */
return -EINVAL;
}
reg_set(client, AK881X_VIDEO_PROCESS1, vp1, 0xf);
return 0;
}
static void spi1_ios(void)
{
u32 val;
reg_set(RCC_APB2ENR, 0x04); /* Activate GPIOA */
/* Configure NSS pin (PA4) */
val = reg_rd(GPIOA);
val &= 0xFFF0FFFF;
val |= 0x00030000; /* output, 50MHz, push-pull */
reg_wr(GPIOA, val);
reg_wr(GPIO_BSRR(GPIOA), (0x01 << 4)); /* Disable SS (nss=1) */
/* Configure SCK pin (PA5) */
val = reg_rd(GPIOA);
val &= 0xFF0FFFFF;
val |= 0x00B00000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOA, val);
/* Configure MOSI pin (PA7) */
val = reg_rd(GPIOA);
val &= 0x0FFFFFFF;
val |= 0xB0000000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOA, val);
/* Configure MISO pin (PA6) */
val = reg_rd(GPIOA);
val &= 0xF0FFFFFF;
val |= 0x04000000; /* input, floating */
reg_wr(GPIOA, val);
}
static void
tda998x_reset(struct tda998x_priv *priv)
{
/* reset audio and i2c master: */
reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
msleep(50);
reg_write(priv, REG_SOFTRESET, 0);
msleep(50);
/* reset transmitter: */
reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
/* PLL registers common configuration */
reg_write(priv, REG_PLL_SERIAL_1, 0x00);
reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
reg_write(priv, REG_PLL_SERIAL_3, 0x00);
reg_write(priv, REG_SERIALIZER, 0x00);
reg_write(priv, REG_BUFFER_OUT, 0x00);
reg_write(priv, REG_PLL_SCG1, 0x00);
reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
reg_write(priv, REG_PLL_SCGN1, 0xfa);
reg_write(priv, REG_PLL_SCGN2, 0x00);
reg_write(priv, REG_PLL_SCGR1, 0x5b);
reg_write(priv, REG_PLL_SCGR2, 0x00);
reg_write(priv, REG_PLL_SCG2, 0x10);
/* Write the default value MUX register */
reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
}
static int tda998x_connector_get_modes(struct drm_connector *connector)
{
struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
struct edid *edid;
int n;
/*
* If we get killed while waiting for the HPD timeout, return
* no modes found: we are not in a restartable path, so we
* can't handle signals gracefully.
*/
if (tda998x_edid_delay_wait(priv))
return 0;
if (priv->rev == TDA19988)
reg_clear(priv, REG_TX4, TX4_PD_RAM);
edid = drm_do_get_edid(connector, read_edid_block, priv);
if (priv->rev == TDA19988)
reg_set(priv, REG_TX4, TX4_PD_RAM);
if (!edid) {
dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
return 0;
}
drm_mode_connector_update_edid_property(connector, edid);
n = drm_add_edid_modes(connector, edid);
priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
kfree(edid);
return n;
}
void time_driver() {
// Set the counter register to zero
reg_write(OSTMR_OSCR_ADDR, 0x0);
// Clear OSSR
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
// Update the counters
g_ms_counter = g_ms_counter + 10;
if(g_ms_counter >= 1000) {
g_ms_counter = 0;
g_s_counter = g_s_counter + 1;
if(g_s_counter >= 60) {
g_s_counter = 0;
g_m_counter = g_m_counter + 1;
if(g_m_counter >= 60) {
g_m_counter = 0;
g_h_counter = g_h_counter + 1;
}
}
}
}
static int _recv(netdev2_t *netdev, char* buf, int len, void *info)
{
encx24j600_t * dev = (encx24j600_t *) netdev;
encx24j600_frame_hdr_t hdr;
(void)info;
lock(dev);
/* read frame header */
sram_op(dev, RRXDATA, dev->rx_next_ptr, (char*)&hdr, sizeof(hdr));
/* hdr.frame_len given by device contains 4 bytes checksum */
size_t payload_len = hdr.frame_len - 4;
if (buf) {
/* read packet (without 4 bytes checksum) */
sram_op(dev, RRXDATA, 0xFFFF, buf, payload_len);
/* decrement available packet count */
cmd(dev, SETPKTDEC);
dev->rx_next_ptr = hdr.rx_next_ptr;
reg_set(dev, ERXTAIL, dev->rx_next_ptr - 2);
}
unlock(dev);
return payload_len;
}
static void spi2_ios(void)
{
u32 val;
reg_set(RCC_APB2ENR, 0x08); /* Activate PortB */
/* Configure NSS pin (PB12) */
val = reg_rd(GPIOB + 0x04);
val &= 0xFFF0FFFF;
val |= 0x00030000; /* output, 50MHz, push-pull */
reg_wr(GPIOB+0x04, val);
reg_wr(GPIO_BSRR(GPIOB), (0x01 << 12)); /* Disable SS (nss=1) */
/* Configure SCK pin (PB13) */
val = reg_rd(GPIOB + 0x04);
val &= 0xFF0FFFFF;
val |= 0x00B00000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOB+0x04, val);
/* Configure MOSI pin (PB15) */
val = reg_rd(GPIOB + 0x04);
val &= 0x0FFFFFFF;
val |= 0xB0000000; /* output, 50MHz, AF, push-pull */
reg_wr(GPIOB+0x04, val);
/* Configure MISO pin (PB14) */
val = reg_rd(GPIOB + 0x04);
val &= 0xF0FFFFFF;
val |= 0x04000000; /* input, floating */
reg_wr(GPIOB + 0x04, val);
}
void C_IRQ_Handler() {
printf("In C_IRQ_Handler\n");
uint32_t next_time;
// unsigned int icpInt = reg_read(INT_ICIP_ADDR);
// printf("icpInt: %x\n", icpInt);
uint32_t OSCR = reg_read(OSTMR_OSCR_ADDR);
// uint32_t OSMR = reg_read(OSTMR_OSMR_ADDR(0));
// uint32_t OSSR = reg_read(OSTMR_OSSR_ADDR);
// printf("OSCR: %d, OSMR: %d, OSSR: %d\n", OSCR, OSMR, OSSR);
if(reg_read(OSTMR_OSSR_ADDR) == 1)
{
// printf("\n\n\n\ndo you get here???\n\n\n\n");
//Incrementing by 10 milliseconds
addTimer(1);
//Increment Match Register
next_time = OSCR + (OSTMR_FREQ_VERDEX);
// printf("New OSMR: %d\n", next_time);
//Store incremented value
reg_write(OSTMR_OSMR_ADDR(0), next_time);
//irq
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
}
//return;
printf("\n leaving C_IRQ_handler\n");
I_Handler_Cleanup();
return;
}
static int
tda998x_encoder_get_modes(struct tda998x_priv *priv,
struct drm_connector *connector)
{
struct edid *edid;
int n;
if (priv->rev == TDA19988)
reg_clear(priv, REG_TX4, TX4_PD_RAM);
edid = drm_do_get_edid(connector, read_edid_block, priv);
if (priv->rev == TDA19988)
reg_set(priv, REG_TX4, TX4_PD_RAM);
if (!edid) {
dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
return 0;
}
drm_mode_connector_update_edid_property(connector, edid);
n = drm_add_edid_modes(connector, edid);
priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
kfree(edid);
return n;
}
void pad_with_false( unsigned limit_reg )
{
unsigned i = arg_count_reg;
while (i < limit_reg)
reg_set( i++, FALSE_OBJ );
}
int C_IRQ_Handler()
{
// get the content of OSCR and OSSR
volatile uint32_t oscr_val = reg_read(OSTMR_OSCR_ADDR);
volatile uint32_t ossr_val = reg_read(OSTMR_OSSR_ADDR);
uint32_t next_match_time;
// If interrupt on OSMR0 happened
if (ossr_val == 1) {
// clear OSSR bit
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
// increment time interval by 10ms
global_time += TIME_INTERVAL;
// increment match register to next match value
next_match_time += oscr_val + OSTMR_FREQ / OSTMR_DIVISOR;
// store value to OSMR0
reg_write(OSTMR_OSMR_ADDR(0), next_match_time);
}
int value=0;
// value=write(regs[0],(void *)regs[1],regs[2]);
return value;
}
/*
* @brief Read/Write to encx24j600's SRAM
*
* @param[in] dev ptr to encx24j600 device handle
* @param[in] cmd either WGPDATA, RGPDATA, WRXDATA, RRXDATA, WUDADATA, RUDADATA
* @param[in] addr SRAM address to start reading. 0xFFFF means continue from old address
* @param ptr pointer to buffer to read from / write to
* @param[in] len nr of bytes to read/write
*/
static void sram_op(encx24j600_t *dev, uint16_t cmd, uint16_t addr, char *ptr, int len)
{
uint16_t reg;
char* in = NULL;
char* out = NULL;
/* determine pointer addr
*
* all SRAM access commands have an
* offset 0x5e to their pointer registers
* */
reg = cmd + 0x5e;
/* read or write? bit 1 tells us */
if (reg & 0x2) {
out = ptr;
} else {
in = ptr;
}
/* set pointer */
if (addr != 0xFFFF) {
reg_set(dev, reg, addr);
}
/* copy data */
cmdn(dev, cmd, in, out, len);
}
void C_Irq_Handler()
{
int icpr = reg_read(INT_ICIP_ADDR);
uint32_t mask = 0x1 << INT_OSTMR_0;
#ifdef debug
printf("enter C_Irq_Handler. \n");
#endif
//uint32_t new_timmer = 0;
if(icpr & mask)
{
#ifdef debug
printf("right irq source (icpr:%d). inside C_Irq_Handler. \n",icpr);
#endif
os_time ++; // 10 ms
//new_timmer = reg_read(OSTMR_OSMR_ADDR(0));
//new_timmer += (osmr_value*10)/1000; // 10 ms
//reg_write(OSTMR_OSMR_ADDR(0), new_timmer);
/* restart */
reg_write(OSTMR_OSCR_ADDR, 0x00);
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
}
else
{
printf("wrong irq source! where (%d) \n", icpr);
}
return;
}
static void
tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
uint8_t *buf, size_t size)
{
reg_clear(priv, REG_DIP_IF_FLAGS, bit);
reg_write_range(priv, addr, buf, size);
reg_set(priv, REG_DIP_IF_FLAGS, bit);
}
/*
* Integer division
* des - destination register
* src1 - dividend
* src2 - divisor
*/
void
_div (int des, int src1, int src2)
{
check (des, TYPE_DES, 1);
check (src1, TYPE_SRC, 2);
check (src2, TYPE_SRC, 3);
/* Check for divide-by-zero error, and divide if possible */
if (mem.registers[src2] == 0) {
printf ("Error: division by zero.\n");
sys_dump (0x0);
sys_halt (0x0);
} else {
reg_set (0x1, des, ((int)mem.registers[src1] / mem.registers[src2]));
reg_set (0x0, 0x1, mem.registers[src1] % mem.registers[src2]);
}
}
/*
* Loads a constant into a register
* des - destination register
* const8 - constant to save
*/
void
_lc (int des, int const8)
{
check (des, TYPE_DES, 1);
check (const8, TYPE_CONST8, 2);
/* Set des to const8 */
reg_set (0x1, des, const8);
}
/*
* Integer subtraction
* des - destination register
* src1 - minuend
* src2 - subtrahend
*/
void
_sub (int des, int src1, int src2)
{
check (des, TYPE_DES, 1);
check (src1, TYPE_SRC, 2);
check (src2, TYPE_SRC, 3);
/* Calculate and store/update r1 */
int diff = mem.registers[src1] + mem.registers[src2];
reg_set (0x1, des, diff);
if (diff > 127) {
reg_set (0x0, 0x1, 1);
} else if (diff < -128) {
reg_set (0x0, 0x1, -1);
} else {
reg_set (0x0, 0x1, 0);
}
}
void cpu_instr_cmpu(const sInstrArgs *iargs) {
octa res;
if(iargs->y < iargs->z)
res = -1;
else if(iargs->y > iargs->z)
res = 1;
else
res = 0;
reg_set(iargs->x,res);
}
/*
* Integer addition
* des - destination register
* src1 - addend
* src2 - addend
*/
void
_add (int des, int src1, int src2)
{
check (des, TYPE_DES, 1);
check (src1, TYPE_SRC, 2);
check (src2, TYPE_SRC, 3);
printf ("add\n");
/* Calculate and store, and update r1 */
int sum = mem.registers[src1] + mem.registers[src2];
reg_set (0x1, des, sum);
if (sum > 127) {
reg_set (0x0, 0x1, 1);
} else if (sum < -128) {
reg_set (0x0, 0x1, -1);
} else {
reg_set (0x0, 0x1, 0);
}
}
//This function is called on all IRQ interrupts
void timer_inc(void)
{
//increment the number of the timer ticks
++num_timer_tick;
//reset the OSSR[M0]bit
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
osmr_count += CLOCKS_PER_TICK;
//reset the OSCR to 0
reg_write(OSTMR_OSMR_ADDR(0), osmr_count);
}
