static int _init(netdev2_t *encdev)
{
encx24j600_t *dev = (encx24j600_t *) encdev;
DEBUG("encx24j600: starting initialization...\n");
/* setup IO */
gpio_init(dev->cs, GPIO_OUT);
gpio_set(dev->cs);
gpio_init_int(dev->int_pin, GPIO_IN_PU, GPIO_FALLING, encx24j600_isr, (void*)dev);
if (spi_init_master(dev->spi, SPI_CONF_FIRST_RISING, ENCX24J600_SPI_SPEED) < 0) {
return -1;
}
lock(dev);
/* initialization procedure as described in data sheet (39935c.pdf) */
do {
do {
xtimer_usleep(ENCX24J600_INIT_DELAY);
reg_set(dev, ENC_EUDAST, 0x1234);
xtimer_usleep(ENCX24J600_INIT_DELAY);
} while (reg_get(dev, ENC_EUDAST) != 0x1234);
while (!(reg_get(dev, ENC_ESTAT) & ENC_CLKRDY));
/* issue System Reset */
cmd(dev, ENC_SETETHRST);
/* make sure initialization finalizes */
xtimer_usleep(1000);
} while (!(reg_get(dev, ENC_EUDAST) == 0x0000));
/* configure flow control */
phy_reg_set(dev, ENC_PHANA, 0x05E1);
reg_set_bits(dev, ENC_ECON2, ENC_AUTOFC);
/* setup receive buffer */
reg_set(dev, ENC_ERXST, RX_BUFFER_START);
reg_set(dev, ENC_ERXTAIL, RX_BUFFER_END);
dev->rx_next_ptr = RX_BUFFER_START;
/* configure receive filter to receive multicast frames */
reg_set_bits(dev, ENC_ERXFCON, ENC_MCEN);
/* setup interrupts */
reg_set_bits(dev, ENC_EIE, ENC_PKTIE | ENC_LINKIE);
cmd(dev, ENC_ENABLERX);
cmd(dev, ENC_SETEIE);
DEBUG("encx24j600: initialization complete.\n");
unlock(dev);
#ifdef MODULE_NETSTATS_L2
memset(&netdev->stats, 0, sizeof(netstats_t));
#endif
return 0;
}
/*
* CPU power management and memory contorller power down
*/
void cpu_reset_all(void)
{
unsigned int reg_data;
void __iomem *pwctrl = __io_address(PRCM_PWCTRL);
/*
for(i=2; i<8; i++)
{
reg_clr_bits(pwctrl, 1 << i);
udelay(10);
reg_set_bits(pwctrl, 1 << i);
udelay(10);
}
*/
/* cpu1 soft reset */
reg_data = (PRCM_PWCTRL_DBG1_SW_RST | PRCM_PWCTRL_DBG0_SW_RST |
PRCM_PWCTRL_WD1_SW_RST | PRCM_PWCTRL_WD0_SW_RST |
PRCM_PWCTRL_NEON1_SW_RST | PRCM_PWCTRL_NEON0_SW_RST |
PRCM_PWCTRL_CPU1_SW_RST);
reg_clr_bits(pwctrl, reg_data);
reg_set_bits(pwctrl, reg_data);
/* cpu0 soft reset */
reg_data = (PRCM_PWCTRL_DBG1_SW_RST | PRCM_PWCTRL_DBG0_SW_RST |
PRCM_PWCTRL_WD1_SW_RST | PRCM_PWCTRL_WD0_SW_RST |
PRCM_PWCTRL_NEON1_SW_RST | PRCM_PWCTRL_NEON0_SW_RST |
PRCM_PWCTRL_CPU0_SW_RST);
reg_clr_bits(pwctrl, reg_data);
reg_set_bits(pwctrl, reg_data);
printk(KERN_NOTICE "cpu reset over!\n");
}
/*clk gating ctl.
*scm_pclk cannot close, if close, all clock can not run.
*/
void clk_gating(void)
{
unsigned int i;
void __iomem *clk1_ctrl = __io_address(PRCM_CLK1_CTRL);
void __iomem *clk2_ctrl = __io_address(PRCM_CLK2_CTRL);
udelay(2000);
for(i = 0; i < 7; i++)
{
reg_clr_bits(clk1_ctrl, 1 << i);
udelay(10);
reg_set_bits(clk1_ctrl, 1 << i);
udelay(10);
}
for(i = 0; i < 30; i++)
{
if(i >= 18 && i<= 20)
continue;
reg_clr_bits(clk2_ctrl, 1 << i);
udelay(10);
reg_set_bits(clk2_ctrl, 1 << i);
udelay(10);
}
printk(KERN_NOTICE "clock gating over!\n");
udelay(80);
}
/*switch cpu freq: 800MHz, 1066MHz, 1200MHz, 1333MHz, 1600MHz, 2000MHz
*software dynamic switch cpu feq:
* must set system freq mode update register [6] = 1
*cpumode: cpu/axi/ahb ddr pll4
*/
void set_cpu_mode(unsigned int cpu_mode)
{
void __iomem *mode_ctrl = __io_address(PRCM_SYSFREQ_MODE_CTRL);
//clr CPU_FREQ_FRESH = 0
reg_clr_bits(mode_ctrl, (1 << 5));
reg_clr_bits(mode_ctrl, PRCM_SYSF_MODE_CPU_MASK);
//set cpu freq
reg_set_bits(mode_ctrl, PRCM_SYSF_MODE_CPU_FREQ_SW_EN | cpu_mode);
//set CPU_FREQ_FRESH = 1
reg_set_bits(mode_ctrl, (1 << 5));
//wait for 100us to stable
udelay(100);
}
/*
* Global software reset control
* posedge trigger a global software reset
* NOTICE: global reset can not reset prcm registers
*/
void prcm_glb_soft_reset(void)
{
void __iomem *ctrl = __io_address(PRCM_RSTCTRL);
reg_clr_bits(ctrl, PRCM_RSTCTRL_GLB_SW_RST); //0
reg_set_bits(ctrl, PRCM_RSTCTRL_GLB_SW_RST);//1
// printk(KERN_EMERG "globle soft reset over!\n");
}
void ns2816_i2sclk_set_rate(unsigned int rate)
{
void __iomem *sel_ctrl = __io_address(PRCM_CLK_SEL_CTRL);
reg_clr_bits(sel_ctrl, PRCM_CLK_SEL_I2S_CLK_MASK);
reg_set_bits(sel_ctrl, rate);
printk(KERN_NOTICE "Already set I2S clock to %d .\n", rate);
}
void prcm_usb_reset(void)
{
unsigned int reg_value = 0;
void __iomem *rst_usb = __io_address(PRCM_RSTCTRL_USB);
reg_clr_bits(rst_usb, PRCM_RSTCTRL_USB_RST); //0
udelay(4);
reg_set_bits(rst_usb, PRCM_RSTCTRL_USB_RST); //1
udelay(800); //keep high to usb work normally
reg_value = PRCM_RSTCTRL_USB_RST_PORT0 | PRCM_RSTCTRL_USB_RST_PORT1 |
PRCM_RSTCTRL_USB_RST_PORT2 | PRCM_RSTCTRL_USB_RST_PORT3 ;
//port reset is level trigger and high trigger reset.
reg_set_bits(rst_usb, reg_value); //1
udelay(100);
reg_clr_bits(rst_usb, reg_value); //0
printk(KERN_NOTICE "usb reset...\n");
}
/* usb ref clk switch
* set switch clk
* reset usb
*/
void prcm_usb_sel_refclk(unsigned int refclk_sel, unsigned int refclk_div)
{
unsigned int reg_value = 0;
void __iomem *usb_refclk = __io_address(PRCM_RSTCTRL_USB_REFCLK);
reg_value = __raw_readl(usb_refclk);
if((refclk_sel == (reg_value & PRCM_RST_CTRL_USB_REFCLK_SEL_MASK) )
&& (refclk_div == (reg_value & PRCM_RST_CTRL_USB_REFCLK_DIV_MASK)))
{
printk(KERN_NOTICE "usb reference clock is already set to what your want! return.\n");
return;
}
reg_clr_bits(usb_refclk, PRCM_RST_CTRL_USB_REFCLK_SEL_MASK);
reg_set_bits(usb_refclk, refclk_sel);
reg_clr_bits(usb_refclk, PRCM_RST_CTRL_USB_REFCLK_DIV_MASK);
reg_set_bits(usb_refclk, refclk_div);
printk(KERN_NOTICE "alread set usb clock, refcle sel is %d, refclk divider is %d .\n"
, refclk_sel, refclk_div);
}
/*
*reset and enable watchdog
*/
void watchdog_reset_enable(void)
{
void __iomem *ctrl = __io_address(PRCM_RSTCTRL);
void __iomem *private_watchdog = __io_address(NS2816_GTIMER_BASE);
unsigned int value = 0;
//enable watchdog reset
reg_set_bits(ctrl, PRCM_RSTCTRL_WDRESET_EN);
//watchdog control register
__raw_writel(0, private_watchdog + NS2816_SYS_WATCHDOG_CONTROL);
//watchdog load register
__raw_writel(0x00200, private_watchdog + NS2816_SYS_WATCHDOG_LOAD);
value = (NS2816_SYS_WATCHDOG_CONTROL_ENABLE | NS2816_SYS_WATCHDOG_CONTROL_MODE);
__raw_writel(value, private_watchdog + NS2816_SYS_WATCHDOG_CONTROL);
}
void prcm_dll_soft_reset(unsigned int i)
{
void __iomem *dll_rst = __io_address(PRCM_RSTCTRL_DLL);
reg_set_bits(dll_rst, (0x1 << i));
}
