void i2c_setup_interrupt(const hw_module_t *port, bool state)
{
if (state) {
// register the IRQ sub-routine
register_interrupt_routine(port->irq_id, port->irq_subroutine);
// enable the IRQ at the ARM core level
enable_interrupt(port->irq_id, CPU_0, 0);
// clear the status register
HW_I2C_I2SR_WR(port->instance, 0);
// and enable the interrupts in the I2C controller
HW_I2C_I2CR(port->instance).B.IIEN = 1;
} else {
// disable the IRQ at the ARM core level
disable_interrupt(port->irq_id, CPU_0);
// and disable the interrupts in the I2C controller
HW_I2C_I2CR(port->instance).B.IIEN = 0;
// clear the status register
HW_I2C_I2SR_WR(port->instance, 0);
}
}
//! This test first starts the secondary CPUs in order from 1 through 3. When each secondary
//! CPU starts, it executes this function. The first thing this function does for secondary CPUs
//! is to enable interrupts for the CPU in the GIC.
//!
//! When the last CPU enters this function, it will start a loop of sending software interrupts
//! to all cores in sequence by sending the first SGI to core 0. As each core handles the SGI,
//! it will print a message and send an SGI to the next CPU in sequence.
void multicore_entry(void * arg)
{
uint32_t cpu_id = cpu_get_current();
int cpuCount = cpu_get_cores();
if (cpuCount == 1)
{
printf("This chip only has one CPU!\n");
return;
}
if (cpu_id != 0)
{
// Enable interrupts on secondary CPUs.
gic_init_cpu();
}
// primary cpu
if (cpu_id == 0)
{
isTestDone = 1;
// register sgi isr
register_interrupt_routine(SW_INTERRUPT_3, SGI3_ISR);
printf("Running the GIC Multicore Test \n");
printf("Starting and sending SGIs to secondary CPUs for \"hello world\" \n\n");
// start second cpu
cpu_start_secondary(1, &multicore_entry, 0);
// cpu0 wait until test is done, that is until cpu3 completes its SGI.
while (isTestDone);
// put other cores back into reset
cpu_disable(1);
cpu_disable(2);
cpu_disable(3);
printf("\nEnd of test\n");
}
// other cpus
else
{
printf("secondary main cpu: %d\n", cpu_id);
if (cpu_id == (cpuCount - 1))
{
// send to cpu_0 to start sgi loop
gic_send_sgi(SW_INTERRUPT_3, 1, kGicSgiFilter_UseTargetList);
}
else
{
cpu_start_secondary(cpu_id + 1, &multicore_entry, 0);
}
// do nothing wait to be interrupted
while (1);
}
}
void uart_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), uint8_t state)
{
uint32_t irq_id = UART_IRQS(instance);
if (state == TRUE) {
/* register the IRQ sub-routine */
register_interrupt_routine(irq_id, irq_subroutine);
/* enable the IRQ */
enable_interrupt(irq_id, CPU_0, 0);
} else
/* disable the IRQ */
disable_interrupt(irq_id, CPU_0);
}
void ipu_ch0_eobnd_interrupt_register(int ipu_index)
{
int irq_id = IPU1_SYNC + (ipu_index - 1) * 2;
// register the IRQ routine
register_interrupt_routine(irq_id, &ipu1_ch0_eobnd_isr);
memset((void *)CH27_EBA0, 0xFF, 1024*768*2);
memset((void *)CH23_EBA0, 0xFF, 1024*768*2);
// enable interrupt
ipu_write_field(ipu_index, IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_0, 1); // enable band mode
ipu_write_field(ipu_index, IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_0, 1); // enable band mode
enable_interrupt(irq_id, CPU_0, 0);
}
void CAN_Ctrl::init(uint32_t baudrate){
if(!initialized){
initialized=true;
can_init(can, CAN_LAST_MB);
imx_flexcan canmodule;
can_set_can_attributes(&canmodule,mapToFlexcanBitrate(baudrate),can);
can_update_bitrate(&canmodule);
for(int i=0;i<CAN_NUMBER_OF_BUFFERS;i++){
can_mb_int_ack(can,i);
}
//configure fifo
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_FEN); //set RFEN
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_BCC);//set IRMQ
HW_FLEXCAN_MCR_CLR(can->instance,BM_FLEXCAN_MCR_IDAM); // filter format A
REG_SET(REG_RXFGMASK(can->base),~0);
//conif RFFN
REG_SET(REG_CTRL2(can->base),0xF <<REG_CTRL2_RFFN_SHIFT);
//configure other flags
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_SRX_DIS); //No self recv
REG_SET(REG_CTRL2(can->base),REG_CTRL2_RRS_MASK);
//configure irq
irq_hdlr_t handler;
uint32_t irqid;
if(this==&CANs[0]){
irqid=IMX_INT_FLEXCAN1;
handler=&CAN1_IRQHandler;
}else if(this==&CANs[1]){
irqid=IMX_INT_FLEXCAN2;
handler=&CAN2_IRQHandler;
}
register_interrupt_routine(irqid,handler);
enable_interrupt(irqid,cpu_get_current(),128);
gic_set_irq_security(irqid,false);
setupFilters();
can_exit_freeze(can);
can_enable_mb_interrupt(can,FIFO_FLAG_DATARDY);
}
}
/*!
* @brief Setup SNVS interrupt.
*
* Enables or disables the related HW module interrupt, and attached the related
* sub-routine into the vector table.
*
* @param port Pointer to the SNVS module structure.
* @param state true to enable or false to disable.
*/
void snvs_srtc_setup_interrupt(void (*irq_subroutine)(void), uint8_t state)
{
uint32_t irq_id = IMX_INT_SNVS;
if (state)
{
// register the IRQ sub-routine
register_interrupt_routine(irq_id, irq_subroutine);
// enable the IRQ
enable_interrupt(irq_id, CPU_0, 0);
}
else
{
// disable the IRQ
disable_interrupt(irq_id, CPU_0);
}
}
void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt)
{
uint32_t irq_id = EPIT_IRQS(instance);
if (enableIt)
{
// register the IRQ sub-routine
register_interrupt_routine(irq_id, irq_subroutine);
// enable the IRQ
enable_interrupt(irq_id, CPU_0, 0);
}
else
{
// disable the IRQ
disable_interrupt(irq_id, CPU_0);
}
}
/*!
* @brief Setup keypad interrupt.
*
* Enables or disables the related HW module interrupt, and attached the related sub-routine
* into the vector table.
*
* @param state Flag indicating whether to enable (true) or disable (false) the interrupt.
*/
void kpp_setup_interrupt(bool state)
{
if (state)
{
// clear status flags and synchronizer chains
kpp_clear_status();
// register the IRQ sub-routine
register_interrupt_routine(IMX_INT_KPP, &kpp_interrupt_routine);
// enable the IRQ
enable_interrupt(IMX_INT_KPP, CPU_0, 0);
}
else
{
// disable the IRQ
disable_interrupt(IMX_INT_KPP, CPU_0);
// clear status flags and synchronizer chains
kpp_clear_status();
}
}
