int main(int argc, char **argv)
{
int cpu;
if (argc && strcmp(argv[0], "bad") != 0) {
lock_ops.lock = gcc_builtin_lock;
lock_ops.unlock = gcc_builtin_unlock;
} else {
lock_ops.lock = none_lock;
lock_ops.unlock = none_unlock;
}
for_each_present_cpu(cpu) {
if (cpu == 0)
continue;
smp_boot_secondary(cpu, test_spinlock);
}
test_spinlock();
while (!cpumask_full(&smp_test_complete))
cpu_relax();
return report_summary();
}
void report_vcf_summary_stats(FILE *stats_fd, void *db, file_stats_t *stats) {
// Write to plain text file
report_summary(stats_fd, stats);
// Write to database (optional)
if (db) {
report_summary_sqlite3((sqlite3 *) db, stats);
}
}
void one_measurement(int seconds, char *workload)
{
create_all_usb_devices();
start_power_measurement();
devices_start_measurement();
start_process_measurement();
start_cpu_measurement();
if (workload && workload[0]) {
if (system(workload))
fprintf(stderr, _("Unknown issue running workload!\n"));
} else {
do_sleep(seconds);
}
end_cpu_measurement();
end_process_measurement();
collect_open_devices();
devices_end_measurement();
end_power_measurement();
process_cpu_data();
process_process_data();
/* output stats */
process_update_display();
report_summary();
w_display_cpu_cstates();
w_display_cpu_pstates();
if (reporttype != REPORT_OFF) {
report_display_cpu_cstates();
report_display_cpu_pstates();
}
report_process_update_display();
tuning_update_display();
end_process_data();
global_joules_consumed();
compute_bundle();
show_report_devices();
report_show_open_devices();
report_devices();
ahci_create_device_stats_table();
store_results(measurement_time);
end_cpu_data();
}
void one_measurement(int seconds, char *workload)
{
create_all_usb_devices();
start_power_measurement();
devices_start_measurement();
start_process_measurement();
start_cpu_measurement();
if (workload && workload[0]) {
system(workload);
} else {
do_sleep(seconds);
}
end_cpu_measurement();
end_process_measurement();
collect_open_devices();
devices_end_measurement();
end_power_measurement();
process_cpu_data();
process_process_data();
/* output stats */
process_update_display();
report_summary();
w_display_cpu_cstates();
w_display_cpu_pstates();
report_display_cpu_cstates();
report_display_cpu_pstates();
report_process_update_display();
tuning_update_display();
end_process_data();
global_joules_consumed();
compute_bundle();
show_report_devices();
report_show_open_devices();
report_devices();
store_results(measurement_time);
end_cpu_data();
}
int main()
{
u64 t1, t2;
t1 = rdtsc();
t2 = rdtsc();
printf("rdtsc latency %u\n", (unsigned)(t2 - t1));
test_wrtsc(0);
test_wrtsc(100000000000ull);
if (check_cpuid_80000001_edx(CPUID_80000001_EDX_RDTSCP)) {
test_rdtscp(0);
test_rdtscp(10);
test_rdtscp(0x100);
} else
printf("rdtscp not supported\n");
return report_summary();
}
int main()
{
u64 t1, t2, t3, t4, t5;
u64 est_delta_time;
if (cpuid(7).b & (1 << 1)) { // IA32_TSC_ADJUST Feature is enabled?
report("IA32_TSC_ADJUST msr initialization",
rdmsr(IA32_TSC_ADJUST) == 0x0);
t3 = 100000000000ull;
t1 = rdtsc();
wrmsr(IA32_TSC_ADJUST, t3);
t2 = rdtsc();
report("IA32_TSC_ADJUST msr read / write",
rdmsr(IA32_TSC_ADJUST) == t3);
report("TSC adjustment for IA32_TSC_ADJUST value",
(t2 - t1) >= t3);
t3 = 0x0;
wrmsr(IA32_TSC_ADJUST, t3);
report("IA32_TSC_ADJUST msr read / write",
rdmsr(IA32_TSC_ADJUST) == t3);
t4 = 100000000000ull;
t1 = rdtsc();
wrtsc(t4);
t2 = rdtsc();
t5 = rdmsr(IA32_TSC_ADJUST);
// est of time between reading tsc and writing tsc,
// (based on IA32_TSC_ADJUST msr value) should be small
est_delta_time = t4 - t5 - t1;
// arbitray 2x latency (wrtsc->rdtsc) threshold
report("IA32_TSC_ADJUST msr adjustment on tsc write",
est_delta_time <= (2 * (t2 - t4)));
}
else {
report("IA32_TSC_ADJUST feature not enabled", true);
}
return report_summary();
}
int main(int ac, char **av)
{
unsigned long i;
unsigned int pkey = 0x2;
unsigned int pkru_ad = 0x10;
unsigned int pkru_wd = 0x20;
if (!(cpuid_indexed(7, 0).c & (1 << X86_FEATURE_PKU))) {
printf("PKU not enabled\n");
return report_summary();
}
setup_vm();
setup_alt_stack();
set_intr_alt_stack(14, pf_tss);
wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_LMA);
for (i = 0; i < USER_BASE; i += PAGE_SIZE) {
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~PT_USER_MASK;
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned long)pkey << PTE_PKEY_BIT);
invlpg((void *)i);
}
for (i = USER_BASE; i < 2 * USER_BASE; i += PAGE_SIZE) {
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) &= ~USER_BASE;
*get_pte(phys_to_virt(read_cr3()), phys_to_virt(i)) |= ((unsigned long)pkey << PTE_PKEY_BIT);
invlpg((void *)i);
}
write_cr4(read_cr4() | X86_CR4_PKE);
write_cr3(read_cr3());
init_test();
set_cr0_wp(1);
write_pkru(pkru_ad);
test = 21;
report("write to supervisor page when pkru is ad and wp == 1", pf_count == 0 && test == 21);
init_test();
set_cr0_wp(0);
write_pkru(pkru_ad);
test = 22;
report("write to supervisor page when pkru is ad and wp == 0", pf_count == 0 && test == 22);
init_test();
set_cr0_wp(1);
write_pkru(pkru_wd);
test = 23;
report("write to supervisor page when pkru is wd and wp == 1", pf_count == 0 && test == 23);
init_test();
set_cr0_wp(0);
write_pkru(pkru_wd);
test = 24;
report("write to supervisor page when pkru is wd and wp == 0", pf_count == 0 && test == 24);
init_test();
write_pkru(pkru_wd);
set_cr0_wp(0);
USER_VAR(test) = 25;
report("write to user page when pkru is wd and wp == 0", pf_count == 0 && test == 25);
init_test();
write_pkru(pkru_wd);
set_cr0_wp(1);
USER_VAR(test) = 26;
report("write to user page when pkru is wd and wp == 1", pf_count == 1 && test == 26 && save == 25);
init_test();
write_pkru(pkru_ad);
(void)USER_VAR(test);
report("read from user page when pkru is ad", pf_count == 1 && save == 26);
// TODO: implicit kernel access from ring 3 (e.g. int)
return report_summary();
}
