static void reset_clocks(void)
{
/* 4MHz MSI raw range 2*/
struct rcc_clock_scale myclock_config = {
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = PWR_SCALE2,
.flash_waitstates = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 4194000,
.apb2_frequency = 4194000,
.msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
};
rcc_clock_setup_msi(&myclock_config);
/* buttons and uarts */
rcc_periph_clock_enable(RCC_GPIOA);
/* user feedback leds */
rcc_periph_clock_enable(RCC_GPIOB);
/* Enable clocks for USART2. */
rcc_periph_clock_enable(RCC_USART2);
/* And a timers for button presses */
rcc_periph_clock_enable(RCC_TIM7);
}
int main(void)
{
reset_clocks();
gpio_setup();
usart_setup();
setup_buttons();
setup_button_press_timer();
printf("we're awake!\n");
setup_rtc();
setup_rtc_wakeup(1);
while (1) {
PWR_CR |= PWR_CR_LPSDSR;
pwr_set_stop_mode();
__WFI();
reset_clocks();
process_state(&state);
}
return 0;
}
int atyfb_xl_init(struct fb_info *info)
{
const struct xl_card_cfg_t * card = &card_cfg[xl_card];
struct atyfb_par *par = (struct atyfb_par *) info->par;
union aty_pll pll;
int i, err;
u32 temp;
aty_st_8(CONFIG_STAT0, 0x85, par);
mdelay(10);
/*
* The following needs to be set before the call
* to var_to_pll() below. They'll be re-set again
* to the same values in aty_init().
*/
par->ref_clk_per = 100000000UL/card->ref_crystal;
par->ram_type = card->mem_type;
info->fix.smem_len = card->mem_size;
if (xl_card == VICTORIA) {
// the MCLK, XCLK are 120MHz on victoria card
par->mclk_per = 1000000/120;
par->xclk_per = 1000000/120;
par->features &= ~M64F_MFB_TIMES_4;
}
/*
* Calculate mclk and xclk dividers, etc. The passed
* pixclock and bpp values don't matter yet, the vclk
* isn't programmed until later.
*/
if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll)))
return err;
aty_st_pll(LVDS_CNTL0, 0x00, par);
aty_st_pll(DLL2_CNTL, card->dll2_cntl, par);
aty_st_pll(V2PLL_CNTL, 0x10, par);
aty_st_pll(MPLL_CNTL, MPLL_GAIN, par);
aty_st_pll(VPLL_CNTL, VPLL_GAIN, par);
aty_st_pll(PLL_VCLK_CNTL, 0x00, par);
aty_st_pll(VFC_CNTL, 0x1B, par);
aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, par);
aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, par);
aty_st_pll(SPLL_CNTL2, 0x03, par);
aty_st_pll(PLL_GEN_CNTL, 0x44, par);
reset_clocks(par, &pll.ct, 0);
mdelay(10);
aty_st_pll(VCLK_POST_DIV, 0x03, par);
aty_st_pll(VCLK0_FB_DIV, 0xDA, par);
aty_st_pll(VCLK_POST_DIV, 0x0F, par);
aty_st_pll(VCLK1_FB_DIV, 0xF5, par);
aty_st_pll(VCLK_POST_DIV, 0x3F, par);
aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, par);
aty_st_pll(VCLK2_FB_DIV, 0x00, par);
aty_st_pll(VCLK_POST_DIV, 0xFF, par);
aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, par);
aty_st_pll(VCLK3_FB_DIV, 0x00, par);
aty_st_8(BUS_CNTL, 0x01, par);
aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, par);
aty_st_le32(CRTC_GEN_CNTL, 0x04000200, par);
aty_st_le16(CONFIG_STAT0, 0x0020, par);
aty_st_le32(MEM_CNTL, 0x10151A33, par);
aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, par);
aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, par);
aty_st_le32(DAC_CNTL, card->dac_cntl, par);
aty_st_le16(GEN_TEST_CNTL, 0x0100, par);
aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, par);
aty_st_le32(MEM_BUF_CNTL, 0x00382848, par);
aty_st_le32(HW_DEBUG, card->hw_debug, par);
aty_st_le16(MEM_ADDR_CONFIG, 0x0000, par);
aty_st_le16(GP_IO+2, 0x0000, par);
aty_st_le16(GEN_TEST_CNTL, 0x0000, par);
aty_st_le16(EXT_DAC_REGS+2, 0x0000, par);
aty_st_le32(CRTC_INT_CNTL, 0x00000000, par);
aty_st_le32(TIMER_CONFIG, 0x00000000, par);
aty_st_le32(0xEC, 0x00000000, par);
aty_st_le32(0xFC, 0x00000000, par);
for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, par);
}
aty_st_le16(CONFIG_STAT0, 0x00A4, par);
mdelay(10);
aty_st_8(BUS_CNTL+1, 0xA0, par);
mdelay(10);
reset_clocks(par, &pll.ct, 1);
mdelay(10);
// something about power management
aty_st_8(LCD_INDEX, 0x08, par);
aty_st_8(LCD_DATA, 0x0A, par);
aty_st_8(LCD_INDEX, 0x08, par);
aty_st_8(LCD_DATA+3, 0x02, par);
aty_st_8(LCD_INDEX, 0x08, par);
aty_st_8(LCD_DATA, 0x0B, par);
mdelay(2);
// enable display requests, enable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
// disable display
aty_st_8(CRTC_GEN_CNTL, 0x40, par);
// disable display requests, disable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
mdelay(10);
aty_st_pll(PLL_YCLK_CNTL, 0x25, par);
aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, par);
aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, par);
aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, par);
aty_st_8(CUSTOM_MACRO_CNTL+1,
(card->custom_macro_cntl>>8) & 0xff, par);
aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, par);
aty_st_le32(MEM_CNTL, card->mem_cntl, par);
aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, par);
aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, par);
aty_st_pll(PLL_YCLK_CNTL, 0x01, par);
mdelay(15);
aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, par);
mdelay(1);
reset_clocks(par, &pll.ct, 0);
mdelay(50);
reset_clocks(par, &pll.ct, 0);
mdelay(50);
// enable extended register block
aty_st_8(BUS_CNTL+3, 0x7B, par);
mdelay(1);
// disable extended register block
aty_st_8(BUS_CNTL+3, 0x73, par);
aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, par);
// disable display requests, disable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
// disable mapping registers in VGA aperture
aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, par) & ~0x04, par);
mdelay(50);
// enable display requests, enable CRTC
aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
// make GPIO's 14,15,16 all inputs
aty_st_8(LCD_INDEX, 0x07, par);
aty_st_8(LCD_DATA+3, 0x00, par);
// enable the display
aty_st_8(CRTC_GEN_CNTL, 0x00, par);
mdelay(17);
// reset the memory controller
aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
mdelay(15);
aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
mdelay(30);
// enable extended register block
aty_st_8(BUS_CNTL+3,
(u8)(aty_ld_8(BUS_CNTL+3, par) | 0x08),
par);
// set FIFO size to 512 (PIO)
aty_st_le32(GUI_CNTL,
aty_ld_le32(GUI_CNTL, par) & ~0x3,
par);
// enable CRT and disable lcd
aty_st_8(LCD_INDEX, 0x01, par);
temp = aty_ld_le32(LCD_DATA, par);
temp = (temp | 0x01) & ~0x02;
aty_st_le32(LCD_DATA, temp, par);
return 0;
}