s32 cellGemInit(vm::cptr<CellGemAttribute> attribute)
{
cellGem.warning("cellGemInit(attribute=*0x%x)", attribute);
const auto gem = fxm::make<gem_t>();
if (!gem)
{
return CELL_GEM_ERROR_ALREADY_INITIALIZED;
}
if (!attribute || !attribute->spurs_addr || attribute->max_connect > CELL_GEM_MAX_NUM)
{
return CELL_GEM_ERROR_INVALID_PARAMETER;
}
gem->attribute = *attribute;
for (auto gem_num = 0; gem_num < CELL_GEM_MAX_NUM; gem_num++)
{
gem->reset_controller(gem_num);
}
// TODO: is this correct?
gem->timer.Start();
return CELL_OK;
}
/**
* Disable control ISR
*/
static void disable_controller()
{
disable_pwm_tbclk();
HRADCs_Info.enable_Sampling = 0;
stop_DMA();
reset_controller();
}
int get_action(double x, /* system variables == state information */
double x_dot,
double theta,
double theta_dot,
double reinf) /* reinforcement signal */
{
int i,j;
double predicted_value; /* max_{b} Q(t, ss, b) */
if (first_time) {
first_time = 0;
reset_controller(); /* set state and action to null values */
for (i = 0; i < NUM_BOXES; i++)
for (j = 0; j < 2; j++)
q_val[i][j] = W_INIT;
printf("... setting learning parameter ALPHA to %.4f.\n", ALPHA);
printf("... setting noise parameter BETA to %.4f.\n", BETA);
printf("... setting discount parameter GAMMA to %.4f.\n", GAMMA);
printf("... random RND_SEED is %d.\n", RND_SEED);
srand(RND_SEED); /* initialize random number generator */
}
prev_state = cur_state;
prev_action = cur_action;
cur_state = get_box(x, x_dot, theta, theta_dot);
if (prev_action != -1) /* Update, but not for first action in trial */
{
if (cur_state == -1)
/* failure state has Q-value of 0, since the value won't be updated */
predicted_value = 0.0;
else if (q_val[cur_state][0] <= q_val[cur_state][1])
predicted_value = q_val[cur_state][1];
else
predicted_value = q_val[cur_state][0];
q_val[prev_state][prev_action]
+= ALPHA * (reinf + GAMMA * predicted_value
- q_val[prev_state][prev_action]);
}
/* Now determine best action */
if (q_val[cur_state][0] + rnd(-BETA, BETA) <= q_val[cur_state][1])
cur_action = 1;
else
cur_action = 0;
return cur_action;
}
/**
* Turn off specified power supply.
*
* @param dummy dummy argument due to ps_module pointer
*/
static void turn_off(uint16_t dummy)
{
disable_pwm_output(MOD_A_ID);
disable_pwm_output(MOD_B_ID);
PIN_OPEN_AC_MAINS_CONTACTOR_MOD_A;
PIN_OPEN_AC_MAINS_CONTACTOR_MOD_B;
DELAY_US(TIMEOUT_AC_MAINS_CONTACTOR_OPENED_MS*1000);
reset_controller();
if(g_ipc_ctom.ps_module[0].ps_status.bit.state != Interlock)
{
g_ipc_ctom.ps_module[0].ps_status.bit.state = Off;
}
}
static void turn_off(uint16_t dummy)
{
disable_pwm_output(0);
disable_pwm_output(1);
disable_pwm_output(2);
disable_pwm_output(3);
disable_pwm_output(4);
disable_pwm_output(5);
disable_pwm_output(6);
disable_pwm_output(7);
reset_controller();
if(g_ipc_ctom.ps_module[0].ps_status.bit.state != Interlock)
{
g_ipc_ctom.ps_module[0].ps_status.bit.state = Off;
}
}
static void reset_hd(void)
{
static int i;
repeat:
if (reset) {
reset = 0;
i = -1;
reset_controller();
} else if (win_result()) {
bad_rw_intr();
if (reset)
goto repeat;
}
i++;
if (i < NR_HD) {
hd_out(i,hd_info[i].sect,hd_info[i].sect,hd_info[i].head-1,
hd_info[i].cyl,WIN_SPECIFY,&reset_hd);
} else
do_hd_request();
}
void main()
{
int action,box,i;
long success,trial;
double x, x_dot, theta, theta_dot,reinf,predicted_value;
FILE *fptr;
fptr=fopen("rand_restart.txt","w");
x=x_dot=theta=theta_dot=rnd(-BETA,BETA);
success=0;
trial=1;
reinf=0.0;
while (success<1000000) /* If the pole doesn't fall during 1-million trials,assume it succcess.*/
{
action=get_action(x,x_dot,theta,theta_dot,reinf);
cart_pole(action,&x,&x_dot,&theta,&theta_dot);
box=get_box(x,x_dot,theta,theta_dot);
if (box==-1)
{ reinf=-1.0;
predicted_value = 0.0;
q_val[prev_state][prev_action]
+= ALPHA * (reinf + GAMMA * predicted_value - q_val[prev_state][prev_action]);
reset_controller();
x=x_dot=theta=theta_dot=rnd(-BETA,BETA);
trial++;
printf("At %d success ,try %d trials\n",success,trial);
fprintf(fptr,"%d\t%d\n",trial,success);
success=0;
}else{
success++;
reinf=0.0;
}
}
printf("Success at %d trials \n",trial);
for (i=0;i<NUM_BOXES;i++)
fprintf(fptr,"%g %g\n",q_val[i][0],q_val[i][1]);
fclose(fptr);
}
s32 cellGemReset(u32 gem_num)
{
cellGem.todo("cellGemReset(gem_num=%d)", gem_num);
auto gem = fxm::get<gem_t>();
if (!gem)
{
return CELL_GEM_ERROR_UNINITIALIZED;
}
if (!check_gem_num(gem_num))
{
return CELL_GEM_ERROR_INVALID_PARAMETER;
}
gem->reset_controller(gem_num);
// TODO: is this correct?
gem->timer.Start();
return CELL_OK;
}
/**
* Main function for this power supply module
*/
void main_fac_2p4s_acdc(void)
{
init_controller();
init_peripherals_drivers();
init_interruptions();
enable_controller();
/// TODO: check why first sync_pulse occurs
g_ipc_ctom.counter_sync_pulse = 0;
/// TODO: include condition for re-initialization
while(1)
{
check_interlocks();
}
turn_off(0);
disable_controller();
term_interruptions();
reset_controller();
term_peripherals_drivers();
}
/**
* Turn power supply on.
*
* @param dummy dummy argument due to ps_module pointer
*/
static void turn_on(uint16_t dummy)
{
#ifdef USE_ITLK
if(g_ipc_ctom.ps_module[0].ps_status.bit.state == Off)
#else
if(g_ipc_ctom.ps_module[0].ps_status.bit.state <= Interlock)
#endif
{
reset_controller();
g_ipc_ctom.ps_module[0].ps_status.bit.state = Initializing;
PIN_CLOSE_AC_MAINS_CONTACTOR_MOD_A;
PIN_CLOSE_AC_MAINS_CONTACTOR_MOD_B;
DELAY_US(TIMEOUT_AC_MAINS_CONTACTOR_CLOSED_MS*1000);
if(!PIN_STATUS_AC_MAINS_CONTACTOR_MOD_A)
{
set_hard_interlock(MOD_A_ID, AC_MAINS_CONTACTOR_FAIL);
}
if(!PIN_STATUS_AC_MAINS_CONTACTOR_MOD_B)
{
set_hard_interlock(MOD_B_ID, AC_MAINS_CONTACTOR_FAIL);
}
if(g_ipc_ctom.ps_module[0].ps_status.bit.state == Initializing)
{
g_ipc_ctom.ps_module[0].ps_status.bit.openloop = OPEN_LOOP;
g_ipc_ctom.ps_module[0].ps_status.bit.state = SlowRef;
enable_pwm_output(MOD_A_ID);
enable_pwm_output(MOD_B_ID);
}
}
}
static void reset_hd(void)
{
static int i;
repeat:
if (reset) {
reset = 0;
i = -1;
reset_controller();
} else {
check_status();
if (reset)
goto repeat;
}
if (++i < NR_HD) {
struct hd_i_struct *disk = &hd_info[i];
disk->special_op = disk->recalibrate = 1;
hd_out(disk,disk->sect,disk->sect,disk->head-1,
disk->cyl,WIN_SPECIFY,&reset_hd);
if (reset)
goto repeat;
} else
hd_request();
}
static void turn_on(uint16_t dummy)
{
check_capbank_undervoltage();
#ifdef USE_ITLK
if(g_ipc_ctom.ps_module[0].ps_status.bit.state == Off)
#else
if(g_ipc_ctom.ps_module[0].ps_status.bit.state <= Interlock)
#endif
{
reset_controller();
g_ipc_ctom.ps_module[0].ps_status.bit.openloop = OPEN_LOOP;
g_ipc_ctom.ps_module[0].ps_status.bit.state = SlowRef;
enable_pwm_output(0);
enable_pwm_output(1);
enable_pwm_output(2);
enable_pwm_output(3);
enable_pwm_output(4);
enable_pwm_output(5);
enable_pwm_output(6);
enable_pwm_output(7);
}
}
static void reset_hd(int nr)
{
reset_controller();
hd_out(nr,hd_info[nr].sect,hd_info[nr].sect,hd_info[nr].head-1,
hd_info[nr].cyl,WIN_SPECIFY,&redo_hd_request);
}
static void init_controller(void)
{
/**
* TODO: initialize WfmRef and Samples Buffer
*/
init_ps_module(&g_ipc_ctom.ps_module[0],
g_ipc_mtoc.ps_module[0].ps_status.bit.model,
&turn_on, &turn_off, &isr_soft_interlock,
&isr_hard_interlock, &reset_interlocks);
init_ps_module(&g_ipc_ctom.ps_module[1],
g_ipc_mtoc.ps_module[1].ps_status.bit.model,
&turn_on, &turn_off, &isr_soft_interlock,
&isr_hard_interlock, &reset_interlocks);
g_ipc_ctom.ps_module[2].ps_status.all = 0;
g_ipc_ctom.ps_module[3].ps_status.all = 0;
init_ipc();
init_control_framework(&g_controller_ctom);
/*************************************/
/** INITIALIZATION OF DSP FRAMEWORK **/
/*************************************/
/**
* name: SRLIM_V_CAPBANK_REFERENCE
* description: Capacitor bank voltage reference slew-rate limiter
* DP class: DSP_SRLim
* in: V_CAPBANK_SETPOINT
* out: V_CAPBANK_REFERENCE
*/
init_dsp_srlim(SRLIM_V_CAPBANK_REFERENCE, MAX_REF_SLEWRATE,
CONTROLLER_FREQ_SAMP, &V_CAPBANK_SETPOINT,
&V_CAPBANK_REFERENCE);
init_controller_module_A();
init_controller_module_B();
/***********************************************/
/** INITIALIZATION OF SIGNAL GENERATOR MODULE **/
/***********************************************/
disable_siggen(&SIGGEN);
init_siggen(&SIGGEN, CONTROLLER_FREQ_SAMP, &V_CAPBANK_REFERENCE);
cfg_siggen(&SIGGEN, g_ipc_mtoc.siggen.type, g_ipc_mtoc.siggen.num_cycles,
g_ipc_mtoc.siggen.freq, g_ipc_mtoc.siggen.amplitude,
g_ipc_mtoc.siggen.offset, g_ipc_mtoc.siggen.aux_param);
/**
* name: SRLIM_SIGGEN_AMP
* description: Signal generator amplitude slew-rate limiter
* DP class: DSP_SRLim
* in: g_ipc_mtoc.siggen.amplitude
* out: g_ipc_ctom.siggen.amplitude
*/
init_dsp_srlim(SRLIM_SIGGEN_AMP, MAX_SR_SIGGEN_AMP,
CONTROLLER_FREQ_SAMP, &g_ipc_mtoc.siggen.amplitude,
&g_ipc_ctom.siggen.amplitude);
/**
* name: SRLIM_SIGGEN_OFFSET
* description: Signal generator offset slew-rate limiter
* DP class: DSP_SRLim
* in: g_ipc_mtoc.siggen.offset
* out: g_ipc_ctom.siggen.offset
*/
init_dsp_srlim(SRLIM_SIGGEN_OFFSET, MAX_SR_SIGGEN_OFFSET,
CONTROLLER_FREQ_SAMP, &g_ipc_mtoc.siggen.offset,
&g_ipc_ctom.siggen.offset);
/************************************/
/** INITIALIZATION OF TIME SLICERS **/
/************************************/
/**
* Time-slicer for WfmRef sweep decimation
*/
cfg_timeslicer(TIMESLICER_WFMREF, WFMREF_DECIMATION);
/**
* Time-slicer for SamplesBuffer
*/
cfg_timeslicer(TIMESLICER_BUFFER, BUFFER_DECIMATION);
/**
* Time-slicer for controller
*/
cfg_timeslicer(TIMESLICER_CONTROLLER,
CONTROLLER_DECIMATION);
init_buffer(BUF_SAMPLES, &g_buf_samples_ctom, SIZE_BUF_SAMPLES_CTOM);
enable_buffer(BUF_SAMPLES);
/**
* Reset all internal variables
*/
reset_controller();
}
static void reset_hd(int nr)
{
reset_controller();
hd_out(nr, _SECT, _SECT, _HEAD - 1, _CYL, WIN_SPECIFY, &do_request);
}
/* DDR sdram init */
void sdram_init(void)
{
int type = VARIABLE;
unsigned int mode;
unsigned int bypass = 0;
unsigned int rate;
#ifdef CONFIG_DDR_TYPE_DDR3
type = DDR3;
#endif
#ifdef CONFIG_DDR_TYPE_LPDDR
type = LPDDR;
#endif
#ifdef CONFIG_DDR_TYPE_LPDDR2
type = LPDDR2;
#endif
#ifdef CONFIG_DDR_TYPE_DDR2
type = DDR2;
#endif
#ifndef CONFIG_DDR_HOST_CC
struct ddrc_reg ddrc;
struct ddrp_reg ddrp;
#ifndef CONFIG_DDR_TYPE_VARIABLE
struct ddr_params ddr_params;
ddr_params_p = &ddr_params;
#else
ddr_params_p = &gd->arch.gi->ddr_params;
ddr_params_p->freq = gd->arch.gi->cpufreq / gd->arch.gi->ddr_div;
#endif
fill_in_params(ddr_params_p, type);
ddr_params_creator(&ddrc, &ddrp, ddr_params_p);
ddr_params_assign(&ddrc, &ddrp, ddr_params_p);
#endif /* CONFIG_DDR_HOST_CC */
dwc_debug("sdram init start\n");
#ifndef CONFIG_FPGA
clk_set_rate(DDR, gd->arch.gi->ddrfreq);
reset_dll();
rate = clk_get_rate(DDR);
#else
rate = gd->arch.gi->ddrfreq;
#endif
#ifdef CONFIG_M200
if(rate <= 150000000)
bypass = 1;
#endif
reset_controller();
#ifdef CONFIG_DDR_AUTO_SELF_REFRESH
ddr_writel(0x0 ,DDRC_AUTOSR_EN);
#endif
/*force CKE1 HIGH*/
ddr_writel(DDRC_CFG_VALUE, DDRC_CFG);
ddr_writel((1 << 1), DDRC_CTRL);
mode = (type << 1) | (bypass & 1);
/* DDR PHY init*/
ddr_phy_init(mode);
dump_ddrp_register();
ddr_writel(0, DDRC_CTRL);
/* DDR Controller init*/
ddr_controller_init();
dump_ddrc_register();
/* DDRC address remap configure*/
// mem_remap();
ddr_writel(ddr_readl(DDRC_STATUS) & ~DDRC_DSTATUS_MISS, DDRC_STATUS);
#ifdef CONFIG_DDR_AUTO_SELF_REFRESH
if(!bypass)
ddr_writel(0 , DDRC_DLP);
ddr_writel(0x1 ,DDRC_AUTOSR_EN);
#endif
dwc_debug("sdram init finished\n");
#undef DDRTYPE
}
static int __devinit lola_create(struct snd_card *card, struct pci_dev *pci,
int dev, struct lola **rchip)
{
struct lola *chip;
int err;
unsigned int dever;
static struct snd_device_ops ops = {
.dev_free = lola_dev_free,
};
*rchip = NULL;
err = pci_enable_device(pci);
if (err < 0)
return err;
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
if (!chip) {
snd_printk(KERN_ERR SFX "cannot allocate chip\n");
pci_disable_device(pci);
return -ENOMEM;
}
spin_lock_init(&chip->reg_lock);
mutex_init(&chip->open_mutex);
chip->card = card;
chip->pci = pci;
chip->irq = -1;
chip->granularity = granularity[dev];
switch (chip->granularity) {
case 8:
chip->sample_rate_max = 48000;
break;
case 16:
chip->sample_rate_max = 96000;
break;
case 32:
chip->sample_rate_max = 192000;
break;
default:
snd_printk(KERN_WARNING SFX
"Invalid granularity %d, reset to %d\n",
chip->granularity, LOLA_GRANULARITY_MAX);
chip->granularity = LOLA_GRANULARITY_MAX;
chip->sample_rate_max = 192000;
break;
}
chip->sample_rate_min = sample_rate_min[dev];
if (chip->sample_rate_min > chip->sample_rate_max) {
snd_printk(KERN_WARNING SFX
"Invalid sample_rate_min %d, reset to 16000\n",
chip->sample_rate_min);
chip->sample_rate_min = 16000;
}
err = pci_request_regions(pci, DRVNAME);
if (err < 0) {
kfree(chip);
pci_disable_device(pci);
return err;
}
chip->bar[0].addr = pci_resource_start(pci, 0);
chip->bar[0].remap_addr = pci_ioremap_bar(pci, 0);
chip->bar[1].addr = pci_resource_start(pci, 2);
chip->bar[1].remap_addr = pci_ioremap_bar(pci, 2);
if (!chip->bar[0].remap_addr || !chip->bar[1].remap_addr) {
snd_printk(KERN_ERR SFX "ioremap error\n");
err = -ENXIO;
goto errout;
}
pci_set_master(pci);
err = reset_controller(chip);
if (err < 0)
goto errout;
if (request_irq(pci->irq, lola_interrupt, IRQF_SHARED,
KBUILD_MODNAME, chip)) {
printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
err = -EBUSY;
goto errout;
}
chip->irq = pci->irq;
synchronize_irq(chip->irq);
dever = lola_readl(chip, BAR1, DEVER);
chip->pcm[CAPT].num_streams = (dever >> 0) & 0x3ff;
chip->pcm[PLAY].num_streams = (dever >> 10) & 0x3ff;
chip->version = (dever >> 24) & 0xff;
snd_printdd(SFX "streams in=%d, out=%d, version=0x%x\n",
chip->pcm[CAPT].num_streams, chip->pcm[PLAY].num_streams,
chip->version);
/* */
if (chip->pcm[CAPT].num_streams > MAX_STREAM_IN_COUNT ||
chip->pcm[PLAY].num_streams > MAX_STREAM_OUT_COUNT ||
(!chip->pcm[CAPT].num_streams &&
!chip->pcm[PLAY].num_streams)) {
printk(KERN_ERR SFX "invalid DEVER = %x\n", dever);
err = -EINVAL;
goto errout;
}
err = setup_corb_rirb(chip);
if (err < 0)
goto errout;
err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
if (err < 0) {
snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
goto errout;
}
strcpy(card->driver, "Lola");
strlcpy(card->shortname, "Digigram Lola", sizeof(card->shortname));
snprintf(card->longname, sizeof(card->longname),
"%s at 0x%lx irq %i",
card->shortname, chip->bar[0].addr, chip->irq);
strcpy(card->mixername, card->shortname);
lola_irq_enable(chip);
chip->initialized = 1;
*rchip = chip;
return 0;
errout:
lola_free(chip);
return err;
}
int main()
{
int action,box,i;
long success,trial;
double x, x_dot, theta, theta_dot,reinf,predicted_value;
FILE *fptr;
FILE *fptr1;
fptr=fopen("rand_restart.txt","w");
fptr1=fopen("output.csv","w");
x=x_dot=theta=theta_dot=rnd(-BETA,BETA);
double angle;
success=0;
trial=1;
reinf=0.0;
double force;
double j,k;
double best_ALPHA=0;
double best_GAMMA=0;
while (success<1000000) /* If the pole doesn't fall during 1-million trials,assume it succcess.*/
{
//getchar();
action=get_action(x,x_dot,theta,theta_dot,reinf);
cart_pole(action,&x,&x_dot,&theta,&theta_dot);
//printf("%d")
if(action==0)
force=10;
else if(action==1)
force=5;
else if(action==2)
force=0;
else if(action==3)
force=-5;
else
force=-10;
fprintf(fptr1,"%.2f,%.2f,%.2f,%.2f,%f\n",x,theta,x_dot,theta_dot,force);
angle=theta*180/3.1415926;
//printf("x%.2f,angle%.2f,%.2f,%.2f,%d\n",x,angle,x_dot,theta_dot,action);
box=get_box(x,x_dot,theta,theta_dot);
if (box==-1)
{ reinf=-1.0;
predicted_value = 0.0;
q_val[prev_state][prev_action]
+= ALPHA * (reinf + GAMMA * predicted_value - q_val[prev_state][prev_action]);
reset_controller();
x=x_dot=theta=theta_dot=rnd(-BETA,BETA);
trial++;
//printf("At %d success ,try %d trials\n",success,trial);
printf("At trial %d : success--->%d (mean last how long)\n",trial,success);
fprintf(fptr,"trials%d\t success%d\n",trial,success);
success=0;
}else{
success++;
reinf=0.0;
/*if(success>1000000-2)
{
printf("asfasdfasdf");
break;
}*/
}
}
printf("If success > 1000000 \n Success at %d trials \n",trial);
for (i=0;i<NUM_BOXES;i++)
fprintf(fptr,"%g %g\n",q_val[i][0],q_val[i][1]);
fclose(fptr);
fclose(fptr1);
system("pause");
}
/*
* Initialise on creation
*/
void initialise_controller() {
reset_controller();
}
void AnimationController::set_skeleton(const Skeleton_CPtr& skeleton)
{
m_skeleton = skeleton;
reset_controller();
}
int main(int argc, char *argv[])
{
float x, /* cart position, meters */
x_dot, /* cart velocity */
theta, /* pole angle, radians */
theta_dot; /* pole angular velocity */
int action; /* 0 for push-left, 1 for push-right */
int steps = 0; /* duration of trial, in 0.02 sec steps */
int failures = 0; /* number of failed trials */
int best_steps = 0; /* number of steps in best trial */
int best_trial = 0; /* trial number of best trial */
void reset_state(float *x, float *x_dot, float *theta, float *theta_dot);
void cart_pole(int action, float *x, float *x_dot,
float *theta, float *theta_dot);
int fail(float x, float x_dot, float theta, float theta_dot);
extern int get_action(float x, float x_dot, float theta, float theta_dot,
float reinforcement);
extern void reset_controller(void);
/* extern void print_controller_info(); */
printf("Driver: %s\n", rcs_driver_id);
if (TILTED)
printf("Pole will have tilted reset,");
else
printf("Pole has normal reset,");
if (JUPITER_GRAV)
printf(" and \"Jupiter\" gravity.\n");
else
printf(" and normal gravity.\n");
if (ECHO_STATE)
{
echo_file = fopen("poledata", "w");
if (echo_file == NULL)
printf("ERROR: Cannot open \"poledata\" for output.\n");
}
if (argc > 1)
RND_SEED = atoi(argv[1]);
else
RND_SEED = 0;
reset_state(&x, &x_dot, &theta, &theta_dot);
/*--- Iterate through the action-learn loop. ---*/
while (steps++ < MAX_STEPS && failures < MAX_FAILURES)
{
action = get_action(x, x_dot, theta, theta_dot, 0.0);
/*--- Apply action to the simulated cart-pole ---*/
cart_pole(action, &x, &x_dot, &theta, &theta_dot);
if (fail(x, x_dot, theta, theta_dot))
{
failures++;
printf("Trial %d was %d steps.\n", failures, steps);
if (steps > best_steps)
{
best_steps = steps;
best_trial = failures;
}
/* Call controller with negative feedback for learning */
get_action(x, x_dot, theta, theta_dot, -1.0);
reset_controller();
reset_state(&x, &x_dot, &theta, &theta_dot);
steps = 0;
}
}
/* Diagnose result */
if (failures == MAX_FAILURES)
{
printf("Pole not balanced. Stopping after %d failures.\n",failures);
printf("High water mark: %d steps in trial %d.\n\n",
best_steps, best_trial);
}
else
printf("Pole balanced successfully for at least %d steps in trial %d.\n\n",
steps - 1, failures + 1);
/* print_controller_info();*/
if (echo_file != NULL)
fclose(echo_file);
return 0;
}
static void reset_hd(int nr)
{
reset_controller();
hd_out(nr, hd_info[nr].sect, hd_info[nr].sect, hd_info[nr].head - 1,
hd_info[nr].cyl, WIN_SPECIFY, recal_intr);
}
int get_moddb(struct q_moddef *qm, int max_c, char *fname, int ignore_host)
{
FILE *fp;
char line[132];
char lookhost[256];
int i,j,foundi,n,nf,nitems,ntry,nfinal;
int adc,ser;
char g0[100],g1[100],g2[100],g3[100],g4[100],g5[100],g6[100],
g7[100],g8[100],g9[100];
int f2,f0;
struct q_moddef qt[MAX_CONTROLLERS];
int test_communications(int bn, int *padc, int *pser);
int reset_controller(int bn);
gethostname(lookhost,sizeof lookhost);
fprintf(fpout,"\n localhost: %s\n",lookhost);
q_nhosts = 0;
q_ncols_raw = -1;
q_nrows_raw = -1;
q_image_size = -1;
if(NULL == (fp = fopen(fname,"r")))
{
fprintf(fperr,"get_moddb: Cannot open file %s\n",fname);
return(0);
}
for(n = 0; n < max_c; n++)
qt[n].q_def = 0;
nf = 0;
while(NULL != fgets(line,sizeof line, fp))
{
for(i = 0; line[i] != '\0'; i++)
if(0 == checkwhite(line[i]))
break;
/*
* Allow the first non-whitespace thing to be a #
*/
if(line[i] == '#')
continue;
/*
* Also allow lines with only white space; ignore them.
*/
if(line[i] == '\0')
continue;
nitems = sscanf(&line[i],"%s %s %s %s %s %s %s %s %s %s",
g0,g1,g2,g3,g4,g5,g6,g7,g8,g9);
if(nitems == 0)
{
fprintf(fperr,"get_moddb: no items found for %s\n",line);
fclose(fp);
return(0);
}
for(n = 0; dg_dir[n] != NULL; n++)
if(0 == (int) strcmp(dg_dir[n], g0))
break;
if(dg_dir[n] == NULL)
{
fprintf(fperr,"get_moddb: %s is an unknown database directive\n",
g0);
fclose(fp);
return(0);
}
switch(n)
{
case 0:
/*
* chip directive
*/
if(nitems != 4)
{
fprintf(fperr,"get_moddb: chip directive, nitems(%d) != 4\n",
nitems);
fclose(fp);
return(0);
}
q_ncols_raw = (int) atoi(g1);
q_nrows_raw = (int) atoi(g2);
q_image_size = (int) atoi(g3);
break;
case 1:
/*
* host directive
*/
if(nitems != 3)
{
fprintf(fperr,"get_moddb: host directive, nitems(%d) != 3)\n",
nitems);
fclose(fp);
return(0);
}
strcpy(q_hostname[q_nhosts], g1);
q_nboards[q_nhosts] = atoi(g2);
q_nhosts++;
break;
case 2:
/*
* module directive
*/
if(nitems != 10)
{
fprintf(fperr,"get_moddb: number (%d) of args not correct\n",
nitems);
fclose(fp);
return(0);
}
if(g1[0] == '?')
f0 = -1;
else
{
f0 = atoi(g1);
if(f0 < 0 || f0 >= max_c)
{
fprintf(fperr,"get_moddb: board num %d not 0 to %d\n",
f0,max_c -1);
fclose(fp);
return(0);
}
}
qt[nf].q_def = 1;
qt[nf].q_type = -1;
if(0 == strcmp(g2,"master"))
qt[nf].q_type = 0;
if(0 == strcmp(g2,"slave"))
qt[nf].q_type = 1;
if(0 == strcmp(g2,"virtual"))
qt[nf].q_type = 2;
if(qt[nf].q_type == -1)
{
fprintf(fperr,"type unknown: %s\n",g2);
fclose(fp);
return(0);
}
qt[nf].q_assign = g4[0];
qt[nf].q_rotate = atoi(g5);
strcpy(qt[nf].q_host, g6);
qt[nf].q_port = atoi(g7);
qt[nf].q_dport = atoi(g8);
qt[nf].q_sport = atoi(g9);
sscanf(g3,"%x",&f2);
if(qt[nf].q_type != 2 && 0 == strcmp(g6, lookhost) && ignore_host == 0)
{
if(f0 == -1)
{
ntry = MAX_CONTROLLERS;
for(j = 0; j < q_nhosts; j++)
if(0 == strcmp(q_hostname[j], g6))
{
ntry = q_nboards[j];
break;
};
for(n = 0; n < ntry; n++)
if(0 == reset_controller(n))
{
if(0<= test_communications(n, &adc, &ser))
{
if(f2 == ser)
{
f0 = n;
break;
}
}
}
if(f0 == -1)
{
fprintf(fperr,"get_moddb: Error: serial number %x not found\n",f2);
fclose(fp);
return(0);
}
}
}
qt[nf].q_bn = f0;
qt[nf].q_serial = f2;
nf++;
break;
}
}
fclose(fp);
for(n = 0; n < nf; n++)
{
if(qt[n].q_bn == -1)
{
for(i = 0; i < nf; i++)
{
foundi = 0;
for(j = 0; j < nf; j++)
if(qt[j].q_bn == i)
foundi = 1;
if(foundi == 0)
{
qt[n].q_bn = i;
break;
}
}
}
}
for(n = 0; n < nf; n++)
qs[qt[n].q_bn] = qt[n];
/*
* Now just return the modules associated with this host
* unless ignore_host is on, in which case return 'em all.
*
* If the hostname "localhost" appears, don't look up this
* machine's hostname, but return all entries matching localhost.
* This will defeat the purpose of having all databases the
* same on all machines, but....
*/
lookhost[0] = '\0';
for(i = 0; i < q_nhosts; i++)
if(0 == strcmp("localhost", q_hostname[i]))
{
strcpy(lookhost,q_hostname[i]);
break;
}
if(lookhost[0] == '\0')
(void) gethostname(lookhost,sizeof lookhost);
nfinal = 0;
for(n = 0; n < nf; n++)
{
if(ignore_host)
{
qm[nfinal++] = qs[n];
}
else
{
if(0 == strcmp(lookhost, qs[n].q_host))
{
qm[nfinal++] = qs[n];
}
}
}
return(nfinal);
}
static void reset_hd(int nr)
{
reset_controller();
//printk("In hd.c reset_hd(int nr):nr is %d,hd_info[nr].sect is %d,hd_info[nr].sect is %d,hd_info[nr].head-1 is %d,hd_info[nr].cyl is %d,WIN_SPECIFY is %d,&recal_intr is %d\n",nr,hd_info[nr].sect,hd_info[nr].sect,hd_info[nr].head-1,hd_info[nr].cyl,WIN_SPECIFY,&recal_intr);
hd_out(nr,hd_info[nr].sect,hd_info[nr].sect,hd_info[nr].head-1,hd_info[nr].cyl,WIN_SPECIFY,&recal_intr);
}
static void init_controller(void)
{
/**
* TODO: initialize WfmRef and Samples Buffer
*/
init_ps_module(&g_ipc_ctom.ps_module[0],
g_ipc_mtoc.ps_module[0].ps_status.bit.model,
&turn_on, &turn_off, &isr_soft_interlock,
&isr_hard_interlock, &reset_interlocks);
g_ipc_ctom.ps_module[1].ps_status.all = 0;
g_ipc_ctom.ps_module[2].ps_status.all = 0;
g_ipc_ctom.ps_module[3].ps_status.all = 0;
init_ipc();
init_control_framework(&g_controller_ctom);
/***********************************************/
/** INITIALIZATION OF SIGNAL GENERATOR MODULE **/
/***********************************************/
disable_siggen(&SIGGEN);
init_siggen(&SIGGEN, ISR_CONTROL_FREQ,
&g_ipc_ctom.ps_module[0].ps_reference);
cfg_siggen(&SIGGEN, g_ipc_mtoc.siggen.type, g_ipc_mtoc.siggen.num_cycles,
g_ipc_mtoc.siggen.freq, g_ipc_mtoc.siggen.amplitude,
g_ipc_mtoc.siggen.offset, g_ipc_mtoc.siggen.aux_param);
/**
* name: SRLIM_SIGGEN_AMP
* description: Signal generator amplitude slew-rate limiter
* DP class: DSP_SRLim
* in: g_ipc_mtoc.siggen.amplitude
* out: g_ipc_ctom.siggen.amplitude
*/
init_dsp_srlim(SRLIM_SIGGEN_AMP, MAX_SR_SIGGEN_AMP, ISR_CONTROL_FREQ,
&g_ipc_mtoc.siggen.amplitude, &g_ipc_ctom.siggen.amplitude);
/**
* name: SRLIM_SIGGEN_OFFSET
* description: Signal generator offset slew-rate limiter
* DP class: DSP_SRLim
* in: g_ipc_mtoc.siggen.offset
* out: g_ipc_ctom.siggen.offset
*/
init_dsp_srlim(SRLIM_SIGGEN_OFFSET, MAX_SR_SIGGEN_OFFSET,
ISR_CONTROL_FREQ, &g_ipc_mtoc.siggen.offset,
&g_ipc_ctom.siggen.offset);
/*************************************************/
/** INITIALIZATION OF LOAD CURRENT CONTROL LOOP **/
/*************************************************/
/**
* name: SRLIM_I_LOAD_REFERENCE
* description: Load current slew-rate limiter
* DP class: DSP_SRLim
* in: I_LOAD_SETPOINT
* out: I_LOAD_REFERENCE
*/
init_dsp_srlim(SRLIM_I_LOAD_REFERENCE, MAX_REF_SLEWRATE, ISR_CONTROL_FREQ,
&I_LOAD_SETPOINT, &I_LOAD_REFERENCE);
/**
* name: ERROR_I_LOAD
* description: Load current reference error
* dsp module: DSP_Error
* +: I_LOAD_REFERENCE
* -: I_LOAD_MEAN
* out: I_LOAD_ERROR
*/
init_dsp_error(ERROR_I_LOAD, &I_LOAD_REFERENCE, &I_LOAD_MEAN, &I_LOAD_ERROR);
/**
* name: PI_CONTROLLER_I_LOAD
* description: Capacitor bank voltage PI controller
* dsp module: DSP_PI
* in: I_LOAD_ERROR
* out: DUTY_CYCLE
*/
init_dsp_pi(PI_CONTROLLER_I_LOAD, KP_I_LOAD, KI_I_LOAD, ISR_CONTROL_FREQ,
PWM_MAX_DUTY, PWM_MIN_DUTY, &I_LOAD_ERROR, &DUTY_CYCLE_MOD_1);
/**
* name: IIR_2P2Z_CONTROLLER_I_LOAD
* description: Load current IIR 2P2Z controller
* DP class: DSP_IIR_2P2Z
* in: net_signals[4]
* out: DUTY_CYCLE
*/
init_dsp_iir_2p2z(IIR_2P2Z_CONTROLLER_I_LOAD,
IIR_2P2Z_CONTROLLER_I_LOAD_COEFFS.b0,
IIR_2P2Z_CONTROLLER_I_LOAD_COEFFS.b1,
IIR_2P2Z_CONTROLLER_I_LOAD_COEFFS.b2,
IIR_2P2Z_CONTROLLER_I_LOAD_COEFFS.a1,
IIR_2P2Z_CONTROLLER_I_LOAD_COEFFS.a2,
PWM_MAX_DUTY, PWM_MIN_DUTY, &I_LOAD_ERROR,
&DUTY_CYCLE_MOD_1);
/************************************/
/** INITIALIZATION OF TIME SLICERS **/
/************************************/
/**
* Time-slicer for WfmRef sweep decimation
*/
cfg_timeslicer(TIMESLICER_WFMREF, WFMREF_DECIMATION);
/**
* Time-slicer for SamplesBuffer
*/
cfg_timeslicer(TIMESLICER_BUFFER, BUFFER_DECIMATION);
/**
* Samples buffer initialization
*/
init_buffer(BUF_SAMPLES, &g_buf_samples_ctom, SIZE_BUF_SAMPLES_CTOM);
enable_buffer(BUF_SAMPLES);
/**
* Reset all internal variables
*/
reset_controller();
}
