static void fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, GLuint target, GLuint eot ) { struct brw_compile *p = &c->func; /* Pass through control information: */ /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */ { brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */ brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_MOV(p, brw_message_reg(base_reg + 1), brw_vec8_grf(1, 0)); brw_pop_insn_state(p); } /* Send framebuffer write message: */ /* send (16) null.0<1>:uw m0 r0.0<8;8,1>:uw 0x85a04000:ud { Align1 EOT } */ brw_fb_WRITE(p, retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW), base_reg, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), target, nr, 0, eot); }
static void emit_pixel_xy(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, const struct brw_reg *arg0) { struct brw_reg r1 = brw_vec1_grf(1, 0); struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW); brw_set_compression_control(p, BRW_COMPRESSION_NONE); /* Calculate pixel centers by adding 1 or 0 to each of the * micro-tile coordinates passed in r1. */ if (mask & WRITEMASK_X) { brw_ADD(p, vec16(retype(dst[0], BRW_REGISTER_TYPE_UW)), stride(suboffset(r1_uw, 4), 2, 4, 0), brw_imm_v(0x10101010)); } if (mask & WRITEMASK_Y) { brw_ADD(p, vec16(retype(dst[1], BRW_REGISTER_TYPE_UW)), stride(suboffset(r1_uw,5), 2, 4, 0), brw_imm_v(0x11001100)); } brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); }
static void emit_wpos_xy(struct brw_wm_compile *c, const struct brw_reg *dst, GLuint mask, const struct brw_reg *arg0) { struct brw_compile *p = &c->func; /* Calculate the pixel offset from window bottom left into destination * X and Y channels. */ if (mask & WRITEMASK_X) { /* X' = X - origin */ brw_ADD(p, dst[0], retype(arg0[0], BRW_REGISTER_TYPE_W), brw_imm_d(0 - c->key.origin_x)); } if (mask & WRITEMASK_Y) { /* Y' = height - (Y - origin_y) = height + origin_y - Y */ brw_ADD(p, dst[1], negate(retype(arg0[1], BRW_REGISTER_TYPE_W)), brw_imm_d(c->key.origin_y + c->key.drawable_height - 1)); } }
static void emit_wpos_xy(struct brw_wm_compile *c, struct prog_instruction *inst) { struct brw_compile *p = &c->func; GLuint mask = inst->DstReg.WriteMask; struct brw_reg src0[2], dst[2]; dst[0] = get_dst_reg(c, inst, 0, 1); dst[1] = get_dst_reg(c, inst, 1, 1); src0[0] = get_src_reg(c, &inst->SrcReg[0], 0, 1); src0[1] = get_src_reg(c, &inst->SrcReg[0], 1, 1); /* Calculate the pixel offset from window bottom left into destination * X and Y channels. */ if (mask & WRITEMASK_X) { /* X' = X - origin_x */ brw_ADD(p, dst[0], retype(src0[0], BRW_REGISTER_TYPE_W), brw_imm_d(0 - c->key.origin_x)); } if (mask & WRITEMASK_Y) { /* Y' = height - (Y - origin_y) = height + origin_y - Y */ brw_ADD(p, dst[1], negate(retype(src0[1], BRW_REGISTER_TYPE_W)), brw_imm_d(c->key.origin_y + c->key.drawable_height - 1)); } }
static void emit_delta_xy(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, const struct brw_reg *arg0, const struct brw_reg *arg1) { struct brw_reg r1 = brw_vec1_grf(1, 0); /* Calc delta X,Y by subtracting origin in r1 from the pixel * centers. */ if (mask & WRITEMASK_X) { brw_ADD(p, dst[0], retype(arg0[0], BRW_REGISTER_TYPE_UW), negate(r1)); } if (mask & WRITEMASK_Y) { brw_ADD(p, dst[1], retype(arg0[1], BRW_REGISTER_TYPE_UW), negate(suboffset(r1,1))); } }
/** * Allocate registers for GS. * * If sol_program is true, then: * * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF * 1 needs to be set aside to hold the streamed vertex buffer indices. * * - The thread will need to use the destination_indices register. */ static void brw_gs_alloc_regs( struct brw_gs_compile *c, GLuint nr_verts, bool sol_program ) { GLuint i = 0,j; /* Register usage is static, precompute here: */ c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; /* Streamed vertex buffer indices */ if (sol_program) c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); /* Payload vertices plus space for more generated vertices: */ for (j = 0; j < nr_verts; j++) { c->reg.vertex[j] = brw_vec4_grf(i, 0); i += c->nr_regs; } c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD); if (sol_program) { c->reg.destination_indices = retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD); } c->prog_data.urb_read_length = c->nr_regs; c->prog_data.total_grf = i; }
static void emit_pixel_xy(struct brw_wm_compile *c, struct prog_instruction *inst) { struct brw_reg r1 = brw_vec1_grf(1, 0); struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW); struct brw_reg dst0, dst1; struct brw_compile *p = &c->func; GLuint mask = inst->DstReg.WriteMask; dst0 = get_dst_reg(c, inst, 0, 1); dst1 = get_dst_reg(c, inst, 1, 1); /* Calculate pixel centers by adding 1 or 0 to each of the * micro-tile coordinates passed in r1. */ if (mask & WRITEMASK_X) { brw_ADD(p, vec8(retype(dst0, BRW_REGISTER_TYPE_UW)), stride(suboffset(r1_uw, 4), 2, 4, 0), brw_imm_v(0x10101010)); } if (mask & WRITEMASK_Y) { brw_ADD(p, vec8(retype(dst1, BRW_REGISTER_TYPE_UW)), stride(suboffset(r1_uw, 5), 2, 4, 0), brw_imm_v(0x11001100)); } }
/* Kill pixel - set execution mask to zero for those pixels which * fail. */ static void emit_kil( struct brw_wm_compile *c, struct brw_reg *arg0) { struct brw_compile *p = &c->func; struct intel_context *intel = &p->brw->intel; struct brw_reg pixelmask; GLuint i, j; if (intel->gen >= 6) pixelmask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); else pixelmask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); for (i = 0; i < 4; i++) { /* Check if we've already done the comparison for this reg * -- common when someone does KIL TEMP.wwww. */ for (j = 0; j < i; j++) { if (memcmp(&arg0[j], &arg0[i], sizeof(arg0[0])) == 0) break; } if (j != i) continue; brw_push_insn_state(p); brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], brw_imm_f(0)); brw_set_predicate_control_flag_value(p, 0xff); brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_AND(p, pixelmask, brw_flag_reg(), pixelmask); brw_pop_insn_state(p); } }
void brw_NOP(struct brw_compile *p) { struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP); brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); brw_set_src1(insn, brw_imm_ud(0x0)); }
void gen8_vec4_generator::generate_scratch_write(vec4_instruction *ir, struct brw_reg dst, struct brw_reg src, struct brw_reg index) { struct brw_reg header = brw_vec8_grf(GEN7_MRF_HACK_START + ir->base_mrf, 0); MOV_RAW(header, brw_vec8_grf(0, 0)); generate_oword_dual_block_offsets(brw_message_reg(ir->base_mrf + 1), index); MOV(retype(brw_message_reg(ir->base_mrf + 2), BRW_REGISTER_TYPE_D), retype(src, BRW_REGISTER_TYPE_D)); /* Each of the 8 channel enables is considered for whether each * dword is written. */ gen8_instruction *send = next_inst(BRW_OPCODE_SEND); gen8_set_dst(brw, send, dst); gen8_set_src0(brw, send, header); gen8_set_pred_control(send, ir->predicate); gen8_set_dp_message(brw, send, GEN7_SFID_DATAPORT_DATA_CACHE, 255, /* binding table index: stateless access */ GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE, BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD, 3, /* mlen */ 0, /* rlen */ true, /* header present */ false); /* EOT */ }
void gen8_vec4_generator::generate_urb_write(vec4_instruction *ir, bool vs) { struct brw_reg header = brw_vec8_grf(GEN7_MRF_HACK_START + ir->base_mrf, 0); /* Copy g0. */ if (vs) MOV_RAW(header, brw_vec8_grf(0, 0)); gen8_instruction *inst; if (!(ir->urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) { /* Enable Channel Masks in the URB_WRITE_OWORD message header */ default_state.access_mode = BRW_ALIGN_1; inst = OR(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5), BRW_REGISTER_TYPE_UD), retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), brw_imm_ud(0xff00)); gen8_set_mask_control(inst, BRW_MASK_DISABLE); default_state.access_mode = BRW_ALIGN_16; } inst = next_inst(BRW_OPCODE_SEND); gen8_set_urb_message(brw, inst, ir->urb_write_flags, ir->mlen, 0, ir->offset, true); gen8_set_dst(brw, inst, brw_null_reg()); gen8_set_src0(brw, inst, header); }
static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim) { struct brw_compile *p = &c->func; struct intel_context *intel = &c->func.brw->intel; if (intel->gen < 6) { brw_MOV(p, get_element_ud(c->reg.R0, 1), brw_imm_ud(num_prim)); brw_ff_sync(p, c->reg.R0, 0, c->reg.R0, 1, /* allocate */ 1, /* response length */ 0 /* eot */); } else { brw_MOV(p, retype(c->reg.temp, BRW_REGISTER_TYPE_UD), retype(c->reg.R0, BRW_REGISTER_TYPE_UD)); brw_MOV(p, get_element_ud(c->reg.temp, 1), brw_imm_ud(num_prim)); brw_ff_sync(p, c->reg.temp, 0, c->reg.temp, 1, /* allocate */ 1, /* response length */ 0 /* eot */); brw_MOV(p, get_element_ud(c->reg.R0, 0), get_element_ud(c->reg.temp, 0)); } }
static void emit_delta_xy(struct brw_wm_compile *c, struct prog_instruction *inst) { struct brw_reg r1 = brw_vec1_grf(1, 0); struct brw_reg dst0, dst1, src0, src1; struct brw_compile *p = &c->func; GLuint mask = inst->DstReg.WriteMask; dst0 = get_dst_reg(c, inst, 0, 1); dst1 = get_dst_reg(c, inst, 1, 1); src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1); src1 = get_src_reg(c, &inst->SrcReg[0], 1, 1); /* Calc delta X,Y by subtracting origin in r1 from the pixel * centers. */ if (mask & WRITEMASK_X) { brw_ADD(p, dst0, retype(src0, BRW_REGISTER_TYPE_UW), negate(r1)); } if (mask & WRITEMASK_Y) { brw_ADD(p, dst1, retype(src1, BRW_REGISTER_TYPE_UW), negate(suboffset(r1,1))); } }
void vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst, struct brw_reg src) { brw_push_insn_state(p); brw_set_access_mode(p, BRW_ALIGN_1); brw_set_mask_control(p, BRW_MASK_DISABLE); /* If we think of the src and dst registers as composed of 8 DWORDs each, * we want to pick up the contents of DWORDs 0 and 4 from src, truncate * them to WORDs, and then pack them into DWORD 2 of dst. * * It's easier to get the EU to do this if we think of the src and dst * registers as composed of 16 WORDS each; then, we want to pick up the * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of * dst. * * We can do that by the following EU instruction: * * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask } */ brw_MOV(p, suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4), stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0)); brw_set_access_mode(p, BRW_ALIGN_16); brw_pop_insn_state(p); }
static void gen_ADD_GRF_GRF_IMM_d(struct brw_codegen *p) { struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D); struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D); brw_ADD(p, g0, g2, brw_imm_d(1)); }
void ObjectEditor::typeChanged(int type){ switch(type){ case 0: retype(EOBJECT); break; case 1: retype(E_PARALAX);break; case 2: retype(E_GAME_RESURS);break; default: break; } }
void brw_ENDIF(struct brw_compile *p, struct brw_instruction *patch_insn) { GLuint br = 1; if (BRW_IS_IGDNG(p->brw)) br = 2; if (p->single_program_flow) { /* In single program flow mode, there's no need to execute an ENDIF, * since we don't need to do any stack operations, and if we're executing * currently, we want to just continue executing. */ struct brw_instruction *next = &p->store[p->nr_insn]; assert(patch_insn->header.opcode == BRW_OPCODE_ADD); patch_insn->bits3.ud = (next - patch_insn) * 16; } else { struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF); brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD)); brw_set_src1(insn, brw_imm_d(0x0)); insn->header.compression_control = BRW_COMPRESSION_NONE; insn->header.execution_size = patch_insn->header.execution_size; insn->header.mask_control = BRW_MASK_ENABLE; insn->header.thread_control = BRW_THREAD_SWITCH; assert(patch_insn->bits3.if_else.jump_count == 0); /* Patch the if or else instructions to point at this or the next * instruction respectively. */ if (patch_insn->header.opcode == BRW_OPCODE_IF) { /* Automagically turn it into an IFF: */ patch_insn->header.opcode = BRW_OPCODE_IFF; patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); patch_insn->bits3.if_else.pop_count = 0; patch_insn->bits3.if_else.pad0 = 0; } else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) { patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1); patch_insn->bits3.if_else.pop_count = 1; patch_insn->bits3.if_else.pad0 = 0; } else { assert(0); } /* Also pop item off the stack in the endif instruction: */ insn->bits3.if_else.jump_count = 0; insn->bits3.if_else.pop_count = 1; insn->bits3.if_else.pad0 = 0; } }
static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) { const struct gen_device_info *devinfo = c->func.devinfo; GLuint i = 0,j; /* Register usage is static, precompute here: */ c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; if (c->key.nr_userclip) { c->reg.fixed_planes = brw_vec4_grf(i, 0); i += (6 + c->key.nr_userclip + 1) / 2; c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2; } else c->prog_data.curb_read_length = 0; /* Payload vertices plus space for more generated vertices: */ for (j = 0; j < 4; j++) { c->reg.vertex[j] = brw_vec4_grf(i, 0); i += c->nr_regs; } c->reg.t = brw_vec1_grf(i, 0); c->reg.t0 = brw_vec1_grf(i, 1); c->reg.t1 = brw_vec1_grf(i, 2); c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); c->reg.plane_equation = brw_vec4_grf(i, 4); i++; c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ c->reg.dp1 = brw_vec1_grf(i, 4); i++; if (!c->key.nr_userclip) { c->reg.fixed_planes = brw_vec8_grf(i, 0); i++; } c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W); i++; if (devinfo->gen == 5) { c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; } c->first_tmp = i; c->last_tmp = i; c->prog_data.urb_read_length = c->nr_regs; /* ? */ c->prog_data.total_grf = i; }
gen8_instruction * gen8_generator::MOV_RAW(struct brw_reg dst, struct brw_reg src0) { gen8_instruction *inst = next_inst(BRW_OPCODE_MOV); gen8_set_dst(brw, inst, retype(dst, BRW_REGISTER_TYPE_UD)); gen8_set_src0(brw, inst, retype(src0, BRW_REGISTER_TYPE_UD)); gen8_set_mask_control(inst, BRW_MASK_DISABLE); return inst; }
/** * Read a float[4] vector from the data port Data Cache (const buffer). * Location (in buffer) should be a multiple of 16. * Used for fetching shader constants. * If relAddr is true, we'll do an indirect fetch using the address register. */ void brw_dp_READ_4( struct brw_compile *p, struct brw_reg dest, GLboolean relAddr, GLuint location, GLuint bind_table_index ) { /* XXX: relAddr not implemented */ GLuint msg_reg_nr = 1; { struct brw_reg b; brw_push_insn_state(p); brw_set_predicate_control(p, BRW_PREDICATE_NONE); brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_mask_control(p, BRW_MASK_DISABLE); /* Setup MRF[1] with location/offset into const buffer */ b = brw_message_reg(msg_reg_nr); b = retype(b, BRW_REGISTER_TYPE_UD); /* XXX I think we're setting all the dwords of MRF[1] to 'location'. * when the docs say only dword[2] should be set. Hmmm. But it works. */ brw_MOV(p, b, brw_imm_ud(location)); brw_pop_insn_state(p); } { struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); insn->header.predicate_control = BRW_PREDICATE_NONE; insn->header.compression_control = BRW_COMPRESSION_NONE; insn->header.destreg__conditionalmod = msg_reg_nr; insn->header.mask_control = BRW_MASK_DISABLE; /* cast dest to a uword[8] vector */ dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW); brw_set_dest(insn, dest); brw_set_src0(insn, brw_null_reg()); brw_set_dp_read_message(p->brw, insn, bind_table_index, 0, /* msg_control (0 means 1 Oword) */ BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ 0, /* source cache = data cache */ 1, /* msg_length */ 1, /* response_length (1 Oword) */ 0); /* eot */ } }
static void brw_gs_emit_vue(struct brw_gs_compile *c, struct brw_reg vert, GLboolean last, GLuint header) { struct brw_compile *p = &c->func; struct intel_context *intel = &c->func.brw->intel; GLboolean allocate = !last; struct brw_reg temp; if (intel->gen < 6) temp = c->reg.R0; else { temp = c->reg.temp; brw_MOV(p, retype(temp, BRW_REGISTER_TYPE_UD), retype(c->reg.R0, BRW_REGISTER_TYPE_UD)); } /* Overwrite PrimType and PrimStart in the message header, for * each vertex in turn: */ brw_MOV(p, get_element_ud(temp, 2), brw_imm_ud(header)); /* Copy the vertex from vertn into m1..mN+1: */ brw_copy8(p, brw_message_reg(1), vert, c->nr_regs); /* Send each vertex as a seperate write to the urb. This is * different to the concept in brw_sf_emit.c, where subsequent * writes are used to build up a single urb entry. Each of these * writes instantiates a seperate urb entry, and a new one must be * allocated each time. */ brw_urb_WRITE(p, allocate ? temp : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), 0, temp, allocate, 1, /* used */ c->nr_regs + 1, /* msg length */ allocate ? 1 : 0, /* response length */ allocate ? 0 : 1, /* eot */ 1, /* writes_complete */ 0, /* urb offset */ BRW_URB_SWIZZLE_NONE); if (intel->gen >= 6 && allocate) brw_MOV(p, get_element_ud(c->reg.R0, 0), get_element_ud(temp, 0)); }
void brw_emit_anyprim_setup( struct brw_sf_compile *c ) { struct brw_compile *p = &c->func; struct brw_context *brw = p->brw; struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0); struct brw_reg payload_attr = get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0); struct brw_reg primmask; int jmp; struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); c->nr_verts = 3; alloc_regs(c); primmask = retype(get_element(c->tmp, 0), BRW_REGISTER_TYPE_UD); brw_MOV(p, primmask, brw_imm_ud(1)); brw_SHL(p, primmask, primmask, payload_prim); brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_TRILIST) | (1<<_3DPRIM_TRISTRIP) | (1<<_3DPRIM_TRIFAN) | (1<<_3DPRIM_TRISTRIP_REVERSE) | (1<<_3DPRIM_POLYGON) | (1<<_3DPRIM_RECTLIST) | (1<<_3DPRIM_TRIFAN_NOSTIPPLE))); brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z); jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; brw_emit_tri_setup(c, false); brw_land_fwd_jump(p, jmp); brw_AND(p, v1_null_ud, primmask, brw_imm_ud((1<<_3DPRIM_LINELIST) | (1<<_3DPRIM_LINESTRIP) | (1<<_3DPRIM_LINELOOP) | (1<<_3DPRIM_LINESTRIP_CONT) | (1<<_3DPRIM_LINESTRIP_BF) | (1<<_3DPRIM_LINESTRIP_CONT_BF))); brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z); jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; brw_emit_line_setup(c, false); brw_land_fwd_jump(p, jmp); brw_AND(p, v1_null_ud, payload_attr, brw_imm_ud(1<<BRW_SPRITE_POINT_ENABLE)); brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_Z); jmp = brw_JMPI(p, brw_imm_d(0), BRW_PREDICATE_NORMAL) - p->store; brw_emit_point_sprite_setup(c, false); brw_land_fwd_jump(p, jmp); brw_emit_point_setup( c, false ); }
/** * Computes the pixel offset from the window origin for gl_FragCoord(). */ void emit_wpos_xy(struct brw_wm_compile *c, const struct brw_reg *dst, GLuint mask, const struct brw_reg *arg0) { struct brw_compile *p = &c->func; struct intel_context *intel = &p->brw->intel; struct brw_reg delta_x = retype(arg0[0], BRW_REGISTER_TYPE_W); struct brw_reg delta_y = retype(arg0[1], BRW_REGISTER_TYPE_W); if (mask & WRITEMASK_X) { if (intel->gen >= 6) { struct brw_reg delta_x_f = retype(delta_x, BRW_REGISTER_TYPE_F); brw_MOV(p, delta_x_f, delta_x); delta_x = delta_x_f; } if (c->fp->program.PixelCenterInteger) { /* X' = X */ brw_MOV(p, dst[0], delta_x); } else { /* X' = X + 0.5 */ brw_ADD(p, dst[0], delta_x, brw_imm_f(0.5)); } } if (mask & WRITEMASK_Y) { if (intel->gen >= 6) { struct brw_reg delta_y_f = retype(delta_y, BRW_REGISTER_TYPE_F); brw_MOV(p, delta_y_f, delta_y); delta_y = delta_y_f; } if (c->fp->program.OriginUpperLeft) { if (c->fp->program.PixelCenterInteger) { /* Y' = Y */ brw_MOV(p, dst[1], delta_y); } else { brw_ADD(p, dst[1], delta_y, brw_imm_f(0.5)); } } else { float center_offset = c->fp->program.PixelCenterInteger ? 0.0 : 0.5; /* Y' = (height - 1) - Y + center */ brw_ADD(p, dst[1], negate(delta_y), brw_imm_f(c->key.drawable_height - 1 + center_offset)); } } }
bool ObjectEditor::createObject(const QString &patch ){ bool test=true; while(test){ test=false; OffAll(); QUrl createname=QFileDialog::getOpenFileUrl(SpaceEngineEvents,"Select base sprite for creating object",QUrl::fromLocalFile(patch),"*.spr"); OnAll(); if(createname.isEmpty()) //(*Projectpatch)+"/"+SPRITE_DIR return false; QString tempPatch= createname.path(); #ifdef Q_OS_WIN tempPatch=tempPatch.right(tempPatch.size()-1); #endif if(ObjectRender!=NULL) removeObject(ObjectRender); ObjectRender=new EObject((*Projectpatch)+"/"+OBJECT_DIR+"/"+createname.fileName().left(createname.fileName().size()-4),EKord(100,100),EKord(0),tempPatch,Edit_Mode); addObject(ObjectRender,this->getMapsList()->front()); if(ObjectRender->getSource()->size()<1){ QMessageBox::information(this->getMain(),"Error","this sprite is empty! selected new sprite!"); test=true; } } ObjectName->setText(ObjectRender->getName()); ObjectRender->setW(ObjectRender->getW()*ObjectRender->getSource()->operator [](0)->width()/ObjectRender->getSource()->operator [](0)->height()); VBoxWidget->setEnabled(true); sizeX->setValue(ObjectRender->getW()); sizeY->setValue(ObjectRender->getH()); updateAnimationsList(); retype(EOBJECT); return true; }
/* Sets the destination channels to 1.0 or 0.0 according to glFrontFacing. */ void emit_frontfacing(struct brw_compile *p, const struct brw_reg *dst, GLuint mask) { struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); GLuint i; if (!(mask & WRITEMASK_XYZW)) return; for (i = 0; i < 4; i++) { if (mask & (1<<i)) { brw_MOV(p, dst[i], brw_imm_f(0.0)); } } /* bit 31 is "primitive is back face", so checking < (1 << 31) gives * us front face */ brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, r1_6ud, brw_imm_ud(1 << 31)); for (i = 0; i < 4; i++) { if (mask & (1<<i)) { brw_MOV(p, dst[i], brw_imm_f(1.0)); } } brw_set_predicate_control_flag_value(p, 0xff); }
void brw_clip_init_clipmask( struct brw_clip_compile *c ) { struct brw_codegen *p = &c->func; struct brw_reg incoming = get_element_ud(c->reg.R0, 2); /* Shift so that lowest outcode bit is rightmost: */ brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26)); if (c->key.nr_userclip) { struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD); /* Rearrange userclip outcodes so that they come directly after * the fixed plane bits. */ if (p->devinfo->gen == 5 || p->devinfo->is_g4x) brw_AND(p, tmp, incoming, brw_imm_ud(0xff<<14)); else brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14)); brw_SHR(p, tmp, tmp, brw_imm_ud(8)); brw_OR(p, c->reg.planemask, c->reg.planemask, tmp); release_tmp(c, tmp); } }
void vec4_generator::generate_gs_get_instance_id(struct brw_reg dst) { /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT * and store into dst.0 & dst.4. So generate the instruction: * * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q } */ brw_push_insn_state(p); brw_set_access_mode(p, BRW_ALIGN_1); dst = retype(dst, BRW_REGISTER_TYPE_UD); struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); brw_SHR(p, dst, stride(r0, 1, 4, 0), brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT)); brw_pop_insn_state(p); }
void vec4_generator::generate_math2_gen4(vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) { /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13 * "Message Payload": * * "Operand0[7]. For the INT DIV functions, this operand is the * denominator." * ... * "Operand1[7]. For the INT DIV functions, this operand is the * numerator." */ bool is_int_div = inst->opcode != SHADER_OPCODE_POW; struct brw_reg &op0 = is_int_div ? src1 : src0; struct brw_reg &op1 = is_int_div ? src0 : src1; brw_push_insn_state(p); brw_set_saturate(p, false); brw_set_predicate_control(p, BRW_PREDICATE_NONE); brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); brw_pop_insn_state(p); brw_math(p, dst, brw_math_function(inst->opcode), inst->base_mrf, op0, BRW_MATH_DATA_VECTOR, BRW_MATH_PRECISION_FULL); }
void brw_blorp_const_color_program::alloc_regs() { int reg = 0; this->R0 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); this->R1 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW); prog_data.first_curbe_grf = reg; clear_rgba = retype(brw_vec4_grf(reg++, 0), BRW_REGISTER_TYPE_F); reg += BRW_BLORP_NUM_PUSH_CONST_REGS; /* Make sure we didn't run out of registers */ assert(reg <= GEN7_MRF_HACK_START); this->base_mrf = 2; }
void vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst, unsigned base_offset, unsigned first_component, const src_reg &indirect_offset) { vec4_instruction *inst; /* Set up the message header to reference the proper parts of the URB */ dst_reg header = dst_reg(this, glsl_type::uvec4_type); inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header, brw_imm_ud(dst.writemask << first_component), indirect_offset); inst->force_writemask_all = true; vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header)); read->offset = base_offset; read->mlen = 1; read->base_mrf = -1; if (first_component) { /* Read into a temporary and copy with a swizzle and writemask. */ read->dst = retype(dst_reg(this, glsl_type::ivec4_type), dst.type); emit(MOV(dst, swizzle(src_reg(read->dst), BRW_SWZ_COMP_INPUT(first_component)))); } }