static void _detime(_t *dp, unsigned count, unsigned char *p) {
/* detime note/channel based events */
if (dp->fw.verbose > 4)
fprintf(stderr, "%d: _detime(%x, [%x, %x, %x, ...]\n", dp->frame, count, p[0], p[1], p[2]);
if (count == 3) {
unsigned char cmd = p[0]&0xF0;
unsigned char channel = (p[0]&0xF)+1;
unsigned char note = p[1];
if (channel == dp->opts.chan && note == dp->opts.note) {
char out;
if (dp->fw.verbose > 4)
fprintf(stderr, "%d: _detime(%x)\n", dp->frame, cmd);
if (cmd == MIDI_NOTE_OFF) /* the end of a dit or a dah */
out = detime_process(&dp->detime, 0, dp->frame);
else if (cmd == MIDI_NOTE_ON) /* the end of an inter-element, inter-letter, or a longer space */
out = detime_process(&dp->detime, 1, dp->frame);
else
return;
if (out != 0) {
if (ring_buffer_writeable(&dp->ring)) {
ring_buffer_put(&dp->ring, 1, &out);
} else {
fprintf(stderr, "keyer_detime: buffer overflow writing \"%c\"\n", out);
}
}
}
}
}
void uart_a0_sendstr_buffered(char str[]) {
while (*str != '\0') {
ring_buffer_put(_uart_a0_tx_ringbuffer_id, str);
str++;
}
event_signal(_uart_a0_tx_start_ev);
}
__interrupt void USCI_A0_ISR(void) {
switch (__even_in_range(UCA0IV, USCI_UART_UCTXCPTIFG)) {
case USCI_NONE:
break;
case USCI_UART_UCRXIFG: {
const char c = UCA0RXBUF;
ring_buffer_put(_uart_a0_rx_ringbuffer_id, &c); // store rcvd char
//uart_a0_putchar_buffered(c); // echo rcvd char
if (c == '\r') { // line break: end of cmd
event_signal(_uart_a0_rx_ev);
}
LPM1_EXIT;
break;
}
case USCI_UART_UCTXIFG:
if (event_signal(_uart_a0_tx_rdy_ev) == -1) {
event_signal(_uart_a0_tx_interrupt_pending_ev);
}
LPM1_EXIT;
break;
case USCI_UART_UCSTTIFG:
break;
case USCI_UART_UCTXCPTIFG:
break;
}
}
static irqreturn_t uart_interrupt(int irq, void *dev_id)
#endif
{
unsigned char reg, ch, i;
for ( i=0; i<DEV_NUM; i++ ) {
reg = inb( ioports[i] + REG_IIR);
if ( reg & IIR_RECEIVED_AVAILABLE ) {
printk("uart_interrupt(): iir:%x rx interrupt\n", reg);
while ( inb(ioports[i]+REG_LSR) & DATA_READY ) {
ch=inb(ioports[i]);
ring_buffer_put (&ring, ch);
}
// To do: schedule the bottom half
tasklet_schedule(&uart_tasklet);
}
else {
printk("uart_interrupt(): iir:%x unknown\n", reg);
}
}
return IRQ_HANDLED;
}
void
ring_buffer_append(RingBuffer *rb, void *obj, int len) {
if(rb->on_evict && rb->written >= rb->capacity) {
rb->on_evict->handler(rb->on_evict, rb->buffer + (rb->written % rb->capacity));
}
ring_buffer_put(rb, rb->written, obj, len);
}
/**
* Writes data into the ring buffer without clobbering. If there isn't
* enough free space then this method will only write what it can and
* will report back what it was able to write.
* @param data The data to put into the buffer.
* @param size The amount of data to put in from the buffer.
* @return The amount of data actually written to the buffer.
*/
size_t ring_buffer_write(struct ring_buff *rb, const void *data,
size_t size)
{
const size_t avail = ring_buffer_bytes_free(rb);
if (avail < size)
size = avail;
return size ? ring_buffer_put(rb, data, size) : 0;
}
void
engine_set_int(Engine *engine, long doc_id, pstring *field, int value) {
//FIXME?!
RingBuffer *rb = dictFetchValue(engine->ints, field);
assert(field);
if(rb == NULL) {
rb = ring_buffer_new(engine->ints_capacity);
dictAdd(engine->ints, field, rb);
}
ring_buffer_put(rb, doc_id * sizeof(int), &value, sizeof(int));
}
/**
* \brief Function for putting a char in the UART buffer
*
* \param data the data to add to the UART buffer and send
*
*/
static inline void uart_putchar(uint8_t data)
{
// Disable interrupts to get exclusive access to ring_buffer_out.
cli();
if (ring_buffer_is_empty(&ring_buffer_out)) {
// First data in buffer, enable data ready interrupt
UCSR0B |= (1 << UDRIE0);
}
// Put data in buffer
ring_buffer_put(&ring_buffer_out, data);
// Re-enable interrupts
sei();
}
static irqreturn_t uart_interrupt(int irq, void *dev_id)
#endif
{
unsigned char reg, ch;
// Recive data from interrupt
reg = inb(PORT_COM1+REG_IIR);
if ( reg & IIR_RECEIVED_AVAILABLE ) {
printk("uart_interrupt(): iir:%x rx interrupt\n", reg);
while ( inb(PORT_COM1+REG_LSR) & DATA_READY ) {
// Read recive character form register and write to ring buffer
ch=inb(PORT_COM1);
ring_buffer_put (&ring, ch);
}
}
else {
printk("uart_interrupt(): iir:%x unknown\n", reg);
}
return IRQ_HANDLED;
}
static irqreturn_t uart_interrupt(int irq, void *dev_id)
#endif
{
unsigned char reg, ch;
reg = inb(PORT_COM1+REG_IIR);
if ( reg & IIR_RECEIVED_AVAILABLE ) {
printk("uart_interrupt(): iir:%x rx interrupt\n", reg);
while ( inb(PORT_COM1+REG_LSR) & DATA_READY ) {
ch=inb(PORT_COM1);
ring_buffer_put (&ring, ch);
}
// To do: schedule the bottom half
}
else {
printk("uart_interrupt(): iir:%x unknown\n", reg);
}
return IRQ_HANDLED;
}
void uart_a0_enqueue_str_buffered(char str[]) {
while (*str != '\0') {
ring_buffer_put(_uart_a0_tx_ringbuffer_id, str);
str++;
}
}
void uart_a0_putchar_buffered(char c) {
ring_buffer_put(_uart_a0_tx_ringbuffer_id, &c);
event_signal(_uart_a0_tx_start_ev);
}
void uart_a0_enqueue_char_buffered(char c) {
ring_buffer_put(_uart_a0_tx_ringbuffer_id, &c);
}
static void _write(_t *data, jack_nframes_t frame, size_t size, unsigned char *buff) {
ring_buffer_put(&data->rb, sizeof(frame), (unsigned char *)&frame);
ring_buffer_put(&data->rb, sizeof(size), (unsigned char *)&size);
ring_buffer_put(&data->rb, size, buff);
}
