static int idtg2_em_handler(struct rio_dev *rdev, UINT8 portnum) { UINT32 regval, em_perrdet, em_ltlerrdet; #ifdef DEBUG_SRIO char achBuffer[80]; #endif rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { /* Service Logical/Transport Layer Error(s) */ if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { /* Implementation specific error reported */ rio_read_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, ®val); #ifdef DEBUG_SRIO sprintf(achBuffer,"RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); sysDebugWriteString(achBuffer); #endif /* Clear implementation specific address capture CSR */ rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { /* Service Port-Level Error(s) */ if (em_perrdet & REM_PED_IMPL_SPEC) { /* Implementation Specific port error reported */ /* Get IS errors reported */ rio_read_config_32(rdev, IDT_PORT_ISERR_DET(portnum), ®val); #ifdef DEBUG_SRIO sprintf(achBuffer,"RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); sysDebugWriteString(achBuffer); #endif /* Clear all implementation specific events */ rio_write_config_32(rdev, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }
static int idtg2_em_handler(struct rio_dev *rdev, u8 portnum) { struct rio_mport *mport = rdev->net->hport; u16 destid = rdev->rswitch->destid; u8 hopcount = rdev->rswitch->hopcount; u32 regval, em_perrdet, em_ltlerrdet; rio_mport_read_config_32(mport, destid, hopcount, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { /* Service Logical/Transport Layer Error(s) */ if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { /* Implementation specific error reported */ rio_mport_read_config_32(mport, destid, hopcount, IDT_ISLTL_ADDRESS_CAP, ®val); pr_debug("RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); /* Clear implementation specific address capture CSR */ rio_mport_write_config_32(mport, destid, hopcount, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_mport_read_config_32(mport, destid, hopcount, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { /* Service Port-Level Error(s) */ if (em_perrdet & REM_PED_IMPL_SPEC) { /* Implementation Specific port error reported */ /* Get IS errors reported */ rio_mport_read_config_32(mport, destid, hopcount, IDT_PORT_ISERR_DET(portnum), ®val); pr_debug("RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); /* Clear all implementation specific events */ rio_mport_write_config_32(mport, destid, hopcount, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }
static int idtcps_probe(struct rio_dev *rdev, const struct rio_device_id *id) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops) { spin_unlock(&rdev->rswitch->lock); return -EINVAL; } rdev->rswitch->ops = &idtcps_switch_ops; if (rdev->do_enum) { /* set TVAL = ~50us */ rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, CPS_NO_ROUTE); } spin_unlock(&rdev->rswitch->lock); return 0; }
static int idtg2_probe(struct rio_dev *rdev, const struct rio_device_id *id) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops) { spin_unlock(&rdev->rswitch->lock); return -EINVAL; } rdev->rswitch->ops = &idtg2_switch_ops; if (rdev->do_enum) { /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); } /* Create device-specific sysfs attributes */ idtg2_sysfs(rdev, true); spin_unlock(&rdev->rswitch->lock); return 0; }
/* * Gen3 switches repeat sending PW messages until a corresponding event flag * is cleared. Use shutdown notification to disable generation of port-write * messages if their destination node is shut down. */ static void idtg3_shutdown(struct rio_dev *rdev) { int i; u32 rval; u16 destid; /* Currently the enumerator node acts also as PW handler */ if (!rdev->do_enum) return; pr_debug("RIO: %s(%s)\n", __func__, rio_name(rdev)); rio_read_config_32(rdev, RIO_PW_ROUTE, &rval); i = RIO_GET_PORT_NUM(rdev->swpinfo); /* Check port-write destination port */ if (!((1 << i) & rval)) return; /* Disable sending port-write event notifications if PW destID * matches to one of the enumerator node */ rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TGT_DEVID, &rval); if (rval & RIO_EM_PW_TGT_DEVID_DEV16) destid = rval >> 16; else
static int idtg3_probe(struct rio_dev *rdev, const struct rio_device_id *id) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops) { spin_unlock(&rdev->rswitch->lock); return -EINVAL; } rdev->rswitch->ops = &idtg3_switch_ops; if (rdev->do_enum) { /* Disable hierarchical routing support: Existing fabric * enumeration/discovery process (see rio-scan.c) uses 8-bit * flat destination ID routing only. */ rio_write_config_32(rdev, 0x5000 + RIO_BC_RT_CTL_CSR, 0); } spin_unlock(&rdev->rswitch->lock); return 0; }
int idtg2_switch_init(struct rio_dev *rdev, int do_enum) { #ifdef DEBUG_SRIO char achBuffer[40]; sprintf(achBuffer,"RIO: %s for %s\n", __func__, rio_name(rdev)); sysDebugWriteString(achBuffer); #endif rdev->rswitch->add_entry = idtg2_route_add_entry; rdev->rswitch->get_entry = idtg2_route_get_entry; rdev->rswitch->clr_table = idtg2_route_clr_table; rdev->rswitch->set_domain = idtg2_set_domain; rdev->rswitch->get_domain = idtg2_get_domain; rdev->rswitch->em_init = idtg2_em_init; rdev->rswitch->em_handle = idtg2_em_handler; if (do_enum) { /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); } return 0; }
static int idtg2_em_handler(struct rio_dev *rdev, u8 portnum) { u32 regval, em_perrdet, em_ltlerrdet; rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); if (em_ltlerrdet) { if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { rio_read_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, ®val); pr_debug("RIO: %s Implementation Specific LTL errors" \ " 0x%x @(0x%x)\n", rio_name(rdev), em_ltlerrdet, regval); rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); } } rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); if (em_perrdet) { if (em_perrdet & REM_PED_IMPL_SPEC) { rio_read_config_32(rdev, IDT_PORT_ISERR_DET(portnum), ®val); pr_debug("RIO: %s Implementation Specific Port" \ " errors 0x%x\n", rio_name(rdev), regval); rio_write_config_32(rdev, IDT_PORT_ISERR_DET(portnum), 0); } } return 0; }
static void idtg3_remove(struct rio_dev *rdev) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops == &idtg3_switch_ops) rdev->rswitch->ops = NULL; spin_unlock(&rdev->rswitch->lock); }
static int tsi568_switch_init(struct rio_dev *rdev, int do_enum) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); rdev->rswitch->add_entry = tsi568_route_add_entry; rdev->rswitch->get_entry = tsi568_route_get_entry; rdev->rswitch->clr_table = tsi568_route_clr_table; rdev->rswitch->set_domain = NULL; rdev->rswitch->get_domain = NULL; rdev->rswitch->em_init = tsi568_em_init; rdev->rswitch->em_handle = NULL; return 0; }
static int idtg2_switch_init(struct rio_dev *rdev, int do_enum) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); rdev->rswitch->add_entry = idtg2_route_add_entry; rdev->rswitch->get_entry = idtg2_route_get_entry; rdev->rswitch->clr_table = idtg2_route_clr_table; rdev->rswitch->set_domain = idtg2_set_domain; rdev->rswitch->get_domain = idtg2_get_domain; rdev->rswitch->em_init = idtg2_em_init; rdev->rswitch->em_handle = idtg2_em_handler; rdev->rswitch->sw_sysfs = idtg2_sysfs; return 0; }
static void idtg2_remove(struct rio_dev *rdev) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); spin_lock(&rdev->rswitch->lock); if (rdev->rswitch->ops != &idtg2_switch_ops) { spin_unlock(&rdev->rswitch->lock); return; } rdev->rswitch->ops = NULL; /* Remove device-specific sysfs attributes */ idtg2_sysfs(rdev, false); spin_unlock(&rdev->rswitch->lock); }
static int idtg2_switch_init(struct rio_dev *rdev, int do_enum) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); rdev->rswitch->add_entry = idtg2_route_add_entry; rdev->rswitch->get_entry = idtg2_route_get_entry; rdev->rswitch->clr_table = idtg2_route_clr_table; rdev->rswitch->set_domain = idtg2_set_domain; rdev->rswitch->get_domain = idtg2_get_domain; rdev->rswitch->em_init = idtg2_em_init; rdev->rswitch->em_handle = idtg2_em_handler; rdev->rswitch->sw_sysfs = idtg2_sysfs; if (do_enum) { /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); } return 0; }
static int idtcps_switch_init(struct rio_dev *rdev, int do_enum) { pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); rdev->rswitch->add_entry = idtcps_route_add_entry; rdev->rswitch->get_entry = idtcps_route_get_entry; rdev->rswitch->clr_table = idtcps_route_clr_table; rdev->rswitch->set_domain = idtcps_set_domain; rdev->rswitch->get_domain = idtcps_get_domain; rdev->rswitch->em_init = NULL; rdev->rswitch->em_handle = NULL; if (do_enum) { /* set TVAL = ~50us */ rio_write_config_32(rdev, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); /* Ensure that default routing is disabled on startup */ rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT, CPS_NO_ROUTE); } return 0; }
static int idtcps_switch_init(struct rio_dev *rdev, int do_enum) { struct rio_mport *mport = rdev->net->hport; u16 destid = rdev->rswitch->destid; u8 hopcount = rdev->rswitch->hopcount; pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); rdev->rswitch->add_entry = idtcps_route_add_entry; rdev->rswitch->get_entry = idtcps_route_get_entry; rdev->rswitch->clr_table = idtcps_route_clr_table; rdev->rswitch->set_domain = idtcps_set_domain; rdev->rswitch->get_domain = idtcps_get_domain; rdev->rswitch->em_init = NULL; rdev->rswitch->em_handle = NULL; if (do_enum) { /* set TVAL = ~50us */ rio_mport_write_config_32(mport, destid, hopcount, rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); } return 0; }