コード例 #1
0
static void __init rk3188_common_clk_init(struct device_node *np)
{
	void __iomem *reg_base;
	struct clk *clk;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: could not map cru region\n", __func__);
		return;
	}

	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	/* xin12m is created by an cru-internal divider */
	clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock xin12m: %ld\n",
			__func__, PTR_ERR(clk));

	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock usb480m: %ld\n",
			__func__, PTR_ERR(clk));

	rockchip_clk_register_branches(common_clk_branches,
				  ARRAY_SIZE(common_clk_branches));
	rockchip_clk_protect_critical(rk3188_critical_clocks,
				      ARRAY_SIZE(rk3188_critical_clocks));

	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
				  ROCKCHIP_SOFTRST_HIWORD_MASK);

	rockchip_register_restart_notifier(RK2928_GLB_SRST_FST);
}
コード例 #2
0
ファイル: clk-rk3188.c プロジェクト: olerem/barebox
static void __init rk3188_common_clk_init(struct device_node *np)
{
	void __iomem *reg_base;
	struct clk *clk;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: could not map cru region\n", __func__);
		return;
	}

	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	/* Fixed-clock should be registered before all others */
	clk=clk_fixed("xin24m",24000000);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock xin24m: %ld\n",
			__func__, PTR_ERR(clk));

	/* xin12m is created by an cru-internal divider */
	clk = clk_fixed_factor("xin12m", "xin24m", 1, 2, 0);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock xin12m: %ld\n",
			__func__, PTR_ERR(clk));

	clk = clk_fixed_factor("usb480m", "xin24m", 20, 1, 0);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock usb480m: %ld\n",
			__func__, PTR_ERR(clk));

	rockchip_clk_register_branches(common_clk_branches,
				  ARRAY_SIZE(common_clk_branches));
	rockchip_clk_protect_critical(rk3188_critical_clocks,
				      ARRAY_SIZE(rk3188_critical_clocks));
}
コード例 #3
0
ファイル: clk-rk3288.c プロジェクト: Seagate/SMR_FS-EXT4
static void __init rk3288_clk_init(struct device_node *np)
{
	void __iomem *reg_base;
	struct clk *clk;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: could not map cru region\n", __func__);
		return;
	}

	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	/* xin12m is created by an cru-internal divider */
	clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock xin12m: %ld\n",
			__func__, PTR_ERR(clk));


	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock usb480m: %ld\n",
			__func__, PTR_ERR(clk));

	clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
					"hclk_vcodec_pre_v", 0, 1, 4);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
			__func__, PTR_ERR(clk));

	/* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock pclk_wdt: %ld\n",
			__func__, PTR_ERR(clk));
	else
		rockchip_clk_add_lookup(clk, PCLK_WDT);

	rockchip_clk_register_plls(rk3288_pll_clks,
				   ARRAY_SIZE(rk3288_pll_clks),
				   RK3288_GRF_SOC_STATUS1);
	rockchip_clk_register_branches(rk3288_clk_branches,
				  ARRAY_SIZE(rk3288_clk_branches));
	rockchip_clk_protect_critical(rk3288_critical_clocks,
				      ARRAY_SIZE(rk3288_critical_clocks));

	rockchip_clk_register_armclk(ARMCLK, "armclk",
			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
			&rk3288_cpuclk_data, rk3288_cpuclk_rates,
			ARRAY_SIZE(rk3288_cpuclk_rates));

	rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
				  ROCKCHIP_SOFTRST_HIWORD_MASK);

	rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
	rk3288_clk_sleep_init(reg_base);
}
コード例 #4
0
ファイル: clk-rk3368.c プロジェクト: AlexShiLucky/linux
static void __init rk3368_clk_init(struct device_node *np)
{
	struct rockchip_clk_provider *ctx;
	void __iomem *reg_base;
	struct clk *clk;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: could not map cru region\n", __func__);
		return;
	}

	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
	if (IS_ERR(ctx)) {
		pr_err("%s: rockchip clk init failed\n", __func__);
		iounmap(reg_base);
		return;
	}

	/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock pclk_wdt: %ld\n",
			__func__, PTR_ERR(clk));
	else
		rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);

	rockchip_clk_register_plls(ctx, rk3368_pll_clks,
				   ARRAY_SIZE(rk3368_pll_clks),
				   RK3368_GRF_SOC_STATUS0);
	rockchip_clk_register_branches(ctx, rk3368_clk_branches,
				  ARRAY_SIZE(rk3368_clk_branches));
	rockchip_clk_protect_critical(rk3368_critical_clocks,
				      ARRAY_SIZE(rk3368_critical_clocks));

	rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
			mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
			&rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
			ARRAY_SIZE(rk3368_cpuclkb_rates));

	rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
			&rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
			ARRAY_SIZE(rk3368_cpuclkl_rates));

	rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
				  ROCKCHIP_SOFTRST_HIWORD_MASK);

	rockchip_register_restart_notifier(ctx, RK3368_GLB_SRST_FST, NULL);

	rockchip_clk_of_add_provider(np, ctx);
}
コード例 #5
0
ファイル: clk-rk3036.c プロジェクト: avagin/linux
static void __init rk3036_clk_init(struct device_node *np)
{
	struct rockchip_clk_provider *ctx;
	void __iomem *reg_base;
	struct clk *clk;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: could not map cru region\n", __func__);
		return;
	}

	/*
	 * Make uart_pll_clk a child of the gpll, as all other sources are
	 * not that usable / stable.
	 */
	writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
		       reg_base + RK2928_CLKSEL_CON(13));

	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
	if (IS_ERR(ctx)) {
		pr_err("%s: rockchip clk init failed\n", __func__);
		iounmap(reg_base);
		return;
	}

	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
	if (IS_ERR(clk))
		pr_warn("%s: could not register clock usb480m: %ld\n",
			__func__, PTR_ERR(clk));

	rockchip_clk_register_plls(ctx, rk3036_pll_clks,
				   ARRAY_SIZE(rk3036_pll_clks),
				   RK3036_GRF_SOC_STATUS0);
	rockchip_clk_register_branches(ctx, rk3036_clk_branches,
				  ARRAY_SIZE(rk3036_clk_branches));
	rockchip_clk_protect_critical(rk3036_critical_clocks,
				      ARRAY_SIZE(rk3036_critical_clocks));

	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
			&rk3036_cpuclk_data, rk3036_cpuclk_rates,
			ARRAY_SIZE(rk3036_cpuclk_rates));

	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
				  ROCKCHIP_SOFTRST_HIWORD_MASK);

	rockchip_register_restart_notifier(ctx, RK2928_GLB_SRST_FST, NULL);

	rockchip_clk_of_add_provider(np, ctx);
}
コード例 #6
0
ファイル: clk-rk3188.c プロジェクト: 020gzh/linux
static void __init rk3188_common_clk_init(struct device_node *np)
{
	void __iomem *reg_base;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: could not map cru region\n", __func__);
		return;
	}

	rockchip_clk_init(np, reg_base, CLK_NR_CLKS);

	rockchip_clk_register_branches(common_clk_branches,
				  ARRAY_SIZE(common_clk_branches));

	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
				  ROCKCHIP_SOFTRST_HIWORD_MASK);

	rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
}
コード例 #7
0
static void __init rk1108_clk_init(struct device_node *np)
{
    struct rockchip_clk_provider *ctx;
    void __iomem *reg_base;

    reg_base = of_iomap(np, 0);
    if (!reg_base) {
        pr_err("%s: could not map cru region\n", __func__);
        return;
    }

    ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
    if (IS_ERR(ctx)) {
        pr_err("%s: rockchip clk init failed\n", __func__);
        iounmap(reg_base);
        return;
    }

    rockchip_clk_register_plls(ctx, rk1108_pll_clks,
                               ARRAY_SIZE(rk1108_pll_clks),
                               RK1108_GRF_SOC_STATUS0);
    rockchip_clk_register_branches(ctx, rk1108_clk_branches,
                                   ARRAY_SIZE(rk1108_clk_branches));
    rockchip_clk_protect_critical(rk1108_critical_clocks,
                                  ARRAY_SIZE(rk1108_critical_clocks));

    rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
                                 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
                                 &rk1108_cpuclk_data, rk1108_cpuclk_rates,
                                 ARRAY_SIZE(rk1108_cpuclk_rates));

    rockchip_register_softrst(np, 13, reg_base + RK1108_SOFTRST_CON(0),
                              ROCKCHIP_SOFTRST_HIWORD_MASK);

    rockchip_register_restart_notifier(ctx, RK1108_GLB_SRST_FST, NULL);

    rockchip_clk_of_add_provider(np, ctx);
}