/***************************************************************************
Function: sWriteTxPrioByte
Purpose: Write a byte of priority transmit data to a channel
Call: sWriteTxPrioByte(ChP,Data)
CHANNEL_T *ChP; Ptr to channel structure
Byte_t Data; The transmit data byte
Return: int: 1 if the bytes is successfully written, otherwise 0.
Comments: The priority byte is transmitted before any data in the Tx FIFO.
Warnings: No context switches are allowed while executing this function.
*/
int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data)
{
Byte_t DWBuf[4]; /* buffer for double word writes */
if(sGetTxCnt(ChP) > 1) /* write it to Tx priority buffer */
{
rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt); /* get priority buffer status */
if(rp_readch1(ChP,_INDX_DATA) & PRI_PEND) /* priority buffer busy */
return(0); /* nothing sent */
le16enc(DWBuf,ChP->TxPrioBuf); /* data byte address */
DWBuf[2] = Data; /* data byte value */
DWBuf[3] = 0; /* priority buffer pointer */
rp_writech4(ChP,_INDX_ADDR,le32dec(DWBuf)); /* write it out */
le16enc(DWBuf,ChP->TxPrioCnt); /* Tx priority count address */
DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
DWBuf[3] = 0; /* priority buffer pointer */
rp_writech4(ChP,_INDX_ADDR,le32dec(DWBuf)); /* write it out */
}
else /* write it to Tx FIFO */
{
sWriteTxByte(ChP,sGetTxRxDataIO(ChP),Data);
}
return(1); /* 1 byte sent */
}
/***************************************************************************
Function: sFlushTxFIFO
Purpose: Flush the Tx FIFO
Call: sFlushTxFIFO(ChP)
CHANNEL_T *ChP; Ptr to channel structure
Return: void
Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
while it is being flushed the receive processor is stopped
and the transmitter is disabled. After these operations a
4 uS delay is done before clearing the pointers to allow
the receive processor to stop. These items are handled inside
this function.
Warnings: No context switches are allowed while executing this function.
*/
void sFlushTxFIFO(CHANNEL_T *ChP)
{
int i;
Byte_t Ch; /* channel number within AIOP */
int TxEnabled; /* TRUE if transmitter enabled */
if(sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
return; /* don't need to flush */
TxEnabled = FALSE;
if(ChP->TxControl[3] & TX_ENABLE)
{
TxEnabled = TRUE;
sDisTransmit(ChP); /* disable transmitter */
}
sStopRxProcessor(ChP); /* stop Rx processor */
for(i = 0; i < 4000/200; i++) /* delay 4 uS to allow proc to stop */
rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
Ch = (Byte_t)sGetChanNum(ChP);
rp_writech1(ChP,_CMD_REG,Ch | RESTXFCNT); /* apply reset Tx FIFO count */
rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Tx FIFO count */
rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
rp_writech2(ChP,_INDX_DATA,0);
if(TxEnabled)
sEnTransmit(ChP); /* enable transmitter */
sStartRxProcessor(ChP); /* restart Rx processor */
}
/***************************************************************************
Function: sFlushRxFIFO
Purpose: Flush the Rx FIFO
Call: sFlushRxFIFO(ChP)
CHANNEL_T *ChP; Ptr to channel structure
Return: void
Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
while it is being flushed the receive processor is stopped
and the transmitter is disabled. After these operations a
4 uS delay is done before clearing the pointers to allow
the receive processor to stop. These items are handled inside
this function.
Warnings: No context switches are allowed while executing this function.
*/
void sFlushRxFIFO(CHANNEL_T *ChP)
{
int i;
Byte_t Ch; /* channel number within AIOP */
int RxFIFOEnabled; /* TRUE if Rx FIFO enabled */
if(sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
return; /* don't need to flush */
RxFIFOEnabled = FALSE;
if(ChP->R[0x32] == 0x08) /* Rx FIFO is enabled */
{
RxFIFOEnabled = TRUE;
sDisRxFIFO(ChP); /* disable it */
for(i=0; i < 2000/200; i++) /* delay 2 uS to allow proc to disable FIFO*/
rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
}
sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
Ch = (Byte_t)sGetChanNum(ChP);
rp_writech1(ChP,_CMD_REG,Ch | RESRXFCNT); /* apply reset Rx FIFO count */
rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Rx FIFO count */
rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
rp_writech2(ChP,_INDX_DATA,0);
rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
rp_writech2(ChP,_INDX_DATA,0);
if(RxFIFOEnabled)
sEnRxFIFO(ChP); /* enable Rx FIFO */
}
/***************************************************************************
Function: sWriteTxPrioByte
Purpose: Write a byte of priority transmit data to a channel
Call: sWriteTxPrioByte(ChP,Data)
CHANNEL_T *ChP; Ptr to channel structure
Byte_t Data; The transmit data byte
Return: int: 1 if the bytes is successfully written, otherwise 0.
Comments: The priority byte is transmitted before any data in the Tx FIFO.
Warnings: No context switches are allowed while executing this function.
*/
int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data)
{
Byte_t DWBuf[4]; /* buffer for double word writes */
Word_t *WordPtr; /* must be far because Win SS != DS */
crit_enter();
if(sGetTxCnt(ChP) > 1) /* write it to Tx priority buffer */
{
rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt); /* get priority buffer status */
if(rp_readch1(ChP,_INDX_DATA) & PRI_PEND) {/* priority buffer busy */
crit_exit();
return(0); /* nothing sent */
}
WordPtr = (Word_t *)(&DWBuf[0]);
*WordPtr = ChP->TxPrioBuf; /* data byte address */
DWBuf[2] = Data; /* data byte value */
rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
*WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
DWBuf[3] = 0; /* priority buffer pointer */
rp_writech4(ChP,_INDX_ADDR,*((DWord_t *)(&DWBuf[0]))); /* write it out */
}
else /* write it to Tx FIFO */
{
sWriteTxByte(ChP,sGetTxRxDataIO(ChP),Data);
}
crit_exit();
return(1); /* 1 byte sent */
}
/***************************************************************************
Function: sDisInterrupts
Purpose: Disable one or more interrupts for a channel
Call: sDisInterrupts(ChP,Flags)
CHANNEL_T *ChP; Ptr to channel structure
Word_t Flags: Interrupt flags, can be any combination
of the following flags:
TXINT_EN: Interrupt on Tx FIFO empty
RXINT_EN: Interrupt on Rx FIFO at trigger level (see
sSetRxTrigger())
SRCINT_EN: Interrupt on SRC (Special Rx Condition)
MCINT_EN: Interrupt on modem input change
CHANINT_EN: Disable channel interrupt signal to the
AIOP's Interrupt Channel Register.
Return: void
Comments: If an interrupt flag is set in Flags, that interrupt will be
disabled. If an interrupt flag is not set in Flags, that
interrupt will not be changed. Interrupts can be enabled with
function sEnInterrupts().
This function clears the appropriate bit for the channel in the AIOP's
Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
this channel's bit from being set in the AIOP's Interrupt Channel
Register.
*/
void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags)
{
Byte_t Mask; /* Interrupt Mask Register */
ChP->RxControl[2] &=
~((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->RxControl));
ChP->TxControl[2] &= ~((Byte_t)Flags & TXINT_EN);
rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxControl));
if(Flags & CHANINT_EN)
{
Mask = rp_readch1(ChP,_INT_MASK) & rp_sBitMapClrTbl[ChP->ChanNum];
rp_writech1(ChP,_INT_MASK,Mask);
}
}
/***************************************************************************
Function: sEnInterrupts
Purpose: Enable one or more interrupts for a channel
Call: sEnInterrupts(ChP,Flags)
CHANNEL_T *ChP; Ptr to channel structure
Word_t Flags: Interrupt enable flags, can be any combination
of the following flags:
TXINT_EN: Interrupt on Tx FIFO empty
RXINT_EN: Interrupt on Rx FIFO at trigger level (see
sSetRxTrigger())
SRCINT_EN: Interrupt on SRC (Special Rx Condition)
MCINT_EN: Interrupt on modem input change
CHANINT_EN: Allow channel interrupt signal to the AIOP's
Interrupt Channel Register.
Return: void
Comments: If an interrupt enable flag is set in Flags, that interrupt will be
enabled. If an interrupt enable flag is not set in Flags, that
interrupt will not be changed. Interrupts can be disabled with
function sDisInterrupts().
This function sets the appropriate bit for the channel in the AIOP's
Interrupt Mask Register if the CHANINT_EN flag is set. This allows
this channel's bit to be set in the AIOP's Interrupt Channel Register.
Interrupts must also be globally enabled before channel interrupts
will be passed on to the host. This is done with function
sEnGlobalInt().
In some cases it may be desirable to disable interrupts globally but
enable channel interrupts. This would allow the global interrupt
status register to be used to determine which AIOPs need service.
*/
void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags)
{
Byte_t Mask; /* Interrupt Mask Register */
ChP->RxControl[2] |=
((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->RxControl[0]);
ChP->TxControl[2] |= ((Byte_t)Flags & TXINT_EN);
rp_writech4(ChP,_INDX_ADDR,*(DWord_t *)&ChP->TxControl[0]);
if(Flags & CHANINT_EN)
{
Mask = rp_readch1(ChP,_INT_MASK) | rp_sBitMapSetTbl[ChP->ChanNum];
rp_writech1(ChP,_INT_MASK,Mask);
}
}
static void rp_do_receive(struct rp_port *rp, struct tty *tp,
CHANNEL_t *cp, unsigned int ChanStatus)
{
unsigned int CharNStat;
int ToRecv, ch, err = 0;
ToRecv = sGetRxCnt(cp);
if(ToRecv == 0)
return;
/* If status indicates there are errored characters in the
FIFO, then enter status mode (a word in FIFO holds
characters and status)
*/
if(ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
if(!(ChanStatus & STATMODE)) {
ChanStatus |= STATMODE;
sEnRxStatusMode(cp);
}
}
/*
if we previously entered status mode then read down the
FIFO one word at a time, pulling apart the character and
the status. Update error counters depending on status.
*/
tty_lock(tp);
if(ChanStatus & STATMODE) {
while(ToRecv) {
CharNStat = rp_readch2(cp,sGetTxRxDataIO(cp));
ch = CharNStat & 0xff;
if((CharNStat & STMBREAK) || (CharNStat & STMFRAMEH))
err |= TRE_FRAMING;
else if (CharNStat & STMPARITYH)
err |= TRE_PARITY;
else if (CharNStat & STMRCVROVRH) {
rp->rp_overflows++;
err |= TRE_OVERRUN;
}
ttydisc_rint(tp, ch, err);
ToRecv--;
}
/*
After emtying FIFO in status mode, turn off status mode
*/
if(sGetRxCnt(cp) == 0) {
sDisRxStatusMode(cp);
}
} else {
ToRecv = sGetRxCnt(cp);
while (ToRecv) {
ch = rp_readch1(cp,sGetTxRxDataIO(cp));
ttydisc_rint(tp, ch & 0xff, err);
ToRecv--;
}
}
ttydisc_rint_done(tp);
tty_unlock(tp);
}
/*
* NOTE: Must be called with tty_token held
*/
static void
rp_do_receive(struct rp_port *rp, struct tty *tp,
CHANNEL_t *cp, unsigned int ChanStatus)
{
unsigned int CharNStat;
int ToRecv, wRecv, ch, ttynocopy;
ASSERT_LWKT_TOKEN_HELD(&tty_token);
ToRecv = sGetRxCnt(cp);
if(ToRecv == 0)
return;
/* If status indicates there are errored characters in the
FIFO, then enter status mode (a word in FIFO holds
characters and status)
*/
if(ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
if(!(ChanStatus & STATMODE)) {
ChanStatus |= STATMODE;
sEnRxStatusMode(cp);
}
}
/*
if we previously entered status mode then read down the
FIFO one word at a time, pulling apart the character and
the status. Update error counters depending on status.
*/
if(ChanStatus & STATMODE) {
while(ToRecv) {
if(tp->t_state & TS_TBLOCK) {
break;
}
CharNStat = rp_readch2(cp,sGetTxRxDataIO(cp));
ch = CharNStat & 0xff;
if((CharNStat & STMBREAK) || (CharNStat & STMFRAMEH))
ch |= TTY_FE;
else if (CharNStat & STMPARITYH)
ch |= TTY_PE;
else if (CharNStat & STMRCVROVRH)
rp->rp_overflows++;
(*linesw[tp->t_line].l_rint)(ch, tp);
ToRecv--;
}
/*
After emtying FIFO in status mode, turn off status mode
*/
if(sGetRxCnt(cp) == 0) {
sDisRxStatusMode(cp);
}
} else {
/*
* Avoid the grotesquely inefficient lineswitch routine
* (ttyinput) in "raw" mode. It usually takes about 450
* instructions (that's without canonical processing or echo!).
* slinput is reasonably fast (usually 40 instructions plus
* call overhead).
*/
ToRecv = sGetRxCnt(cp);
if ( tp->t_state & TS_CAN_BYPASS_L_RINT ) {
if ( ToRecv > RXFIFO_SIZE ) {
ToRecv = RXFIFO_SIZE;
}
wRecv = ToRecv >> 1;
if ( wRecv ) {
rp_readmultich2(cp,sGetTxRxDataIO(cp),(u_int16_t *)rp->RxBuf,wRecv);
}
if ( ToRecv & 1 ) {
((unsigned char *)rp->RxBuf)[(ToRecv-1)] = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
}
tk_nin += ToRecv;
tk_rawcc += ToRecv;
tp->t_rawcc += ToRecv;
ttynocopy = b_to_q((char *)rp->RxBuf, ToRecv, &tp->t_rawq);
ttwakeup(tp);
} else {
while (ToRecv) {
if(tp->t_state & TS_TBLOCK) {
break;
}
ch = (u_char) rp_readch1(cp,sGetTxRxDataIO(cp));
crit_enter();
(*linesw[tp->t_line].l_rint)(ch, tp);
crit_exit();
ToRecv--;
}
}
}