int fh_gpio_probe(void *priv_data) { struct fh_gpio_obj *gpio_obj = (struct fh_gpio_obj *)priv_data; int i; if (gpio_obj->id == 0) { rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0"); } else if (gpio_obj->id == 1) { rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1"); } rt_hw_interrupt_umask(gpio_obj->irq); for (i = 0; i < 32; i++) { irq_desc[NR_INTERNAL_IRQS + 32 * gpio_obj->id + i].param = gpio_obj; } return 0; }
/** * This function initializes console * */ void rt_hw_console_init(void) { rt_cga_init(); rt_serial_init(); init_keyboard(); /* install keyboard isr */ rt_hw_interrupt_install(INTKEYBOARD, rt_console_isr, RT_NULL, "kbd"); rt_hw_interrupt_umask(INTKEYBOARD); rt_hw_interrupt_install(INTUART0_RX, rt_console_isr, RT_NULL, "COM1"); rt_hw_interrupt_umask(INTUART0_RX); console_device.type = RT_Device_Class_Char; console_device.rx_indicate = RT_NULL; console_device.tx_complete = RT_NULL; console_device.init = rt_console_init; console_device.open = rt_console_open; console_device.close = rt_console_close; console_device.read = rt_console_read; console_device.write = rt_console_write; console_device.control = rt_console_control; console_device.user_data = RT_NULL; /* register a character device */ rt_device_register(&console_device, "console", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); }
int rt_hw_timer_init(void) { uint32_t freq; // Make sure the timer is off. HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0; HW_ARMGLOBALTIMER_CONTROL.B.FCR0 =1; HW_ARMGLOBALTIMER_CONTROL.B.FCR1 =0; HW_ARMGLOBALTIMER_CONTROL.B.DBG_ENABLE =0; // Clear counter. HW_ARMGLOBALTIMER_COUNTER_HI_WR(0); HW_ARMGLOBALTIMER_COUNTER_LO_WR(0); // Now turn on the timer. HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1; freq = get_main_clock(IPG_CLK); epit_init(HW_EPIT1, CLKSRC_IPG_CLK, freq / 1000000, SET_AND_FORGET, 10000, WAIT_MODE_EN | STOP_MODE_EN); epit_counter_enable(HW_EPIT1, 10000, IRQ_MODE); rt_hw_interrupt_install(IMX_INT_EPIT1, rt_hw_timer_isr, RT_NULL, "tick"); rt_hw_interrupt_umask(IMX_INT_EPIT1); return 0; }
int davinci_i2c_init(char *bus_name) { struct rt_i2c_bus_device *bus; struct davinci_i2c_dev *dev; int r; bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); if (bus == RT_NULL) { rt_kprintf("rt_malloc failed\n"); return -RT_ENOMEM; } rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); bus->ops = &bus_ops; bus->timeout = DAVINCI_I2C_TIMEOUT; dev = rt_malloc(sizeof(struct davinci_i2c_dev)); if (!dev) { r = -RT_ENOMEM; goto err; } rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev)); rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO); dev->irq = IRQ_I2C; dev->clk = clk_get("I2CCLK"); if (dev->clk == RT_NULL) { r = -RT_ERROR; goto err1; } psc_change_state(DAVINCI_DM365_LPSC_I2C, 3); dev->base = DAVINCI_I2C_BASE; dev->bus_freq = 100; dev->bus_delay = 0; bus->priv = dev; i2c_davinci_init(dev); rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C"); rt_hw_interrupt_umask(dev->irq); return rt_i2c_bus_device_register(bus, bus_name); err1: rt_free(dev); err: rt_free(bus); return r; }
/* RT-Thread Device Interface */ static rt_err_t rtgui_touch_init(rt_device_t dev) { /* init touch screen structure */ rt_memset(&ts, 0, sizeof(struct s3c2410ts)); ts.delay = 50000; ts.presc = 9; ts.shift = 2; ts.count = 0; ts.xp = ts.yp = 0; ADCCON = S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(ts.presc); ADCDLY = ts.delay; ADCTSC = WAIT4INT(0); rt_hw_interrupt_install(INTADC, rt_touch_handler, RT_NULL); rt_hw_interrupt_umask(INTADC); /* clear interrupt */ INTPND |= (1ul << INTADC); SUBSRCPND |= BIT_SUB_TC; SUBSRCPND |= BIT_SUB_ADC; /* install interrupt handler */ INTSUBMSK &= ~BIT_SUB_ADC; INTSUBMSK &= ~BIT_SUB_TC; touch->first_down_report = RT_TRUE; return RT_EOK; }
/** * This function will init timer0 for system ticks */ void rt_hw_timer_init() { /* timer0, input clocks 24MHz */ volatile timer_regs_t *regs = (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE; /*disable timer*/ regs->tcr &= ~(0x3UL << 6); //TIMMODE 32BIT UNCHAINED MODE regs->tgcr |=(0x1UL << 2); /*not in reset timer */ regs->tgcr |= (0x1UL << 0); //regs->tgcr &= ~(0x1UL << 1); /* set Period Registers */ regs->prd12 = 24000000/RT_TICK_PER_SECOND; regs->tim12 = 0; /* Set enable mode */ regs->tcr |= (0x2UL << 6); //period mode /* install interrupt handler */ rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler, RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12 rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2 }
int fh_wdt_probe(void *priv_data) { rt_watchdog_t *wdt_dev; struct wdt_driver *wdt_drv; struct fh_wdt_obj *wdt_obj = (struct fh_wdt_obj *)priv_data; wdt_drv = (struct wdt_driver *)rt_malloc(sizeof(struct wdt_driver)); rt_memset(wdt_drv, 0, sizeof(struct wdt_driver)); wdt_drv->priv = wdt_obj; rt_hw_interrupt_install(wdt_obj->irq, fh_wdt_interrupt, (void *)wdt_drv, "wdt_irq"); rt_hw_interrupt_umask(wdt_obj->irq); // todo: clk wdt_dev = (rt_watchdog_t *)rt_malloc(sizeof(rt_watchdog_t)); if (wdt_dev == RT_NULL) { rt_kprintf("ERROR: %s rt_watchdog_t malloc failed\n", __func__); } wdt_dev->ops = &fh_watchdog_ops; rt_hw_watchdog_register(wdt_dev, "fh_wdt", RT_DEVICE_OFLAG_RDWR, wdt_drv); return 0; }
int rt_hw_gpio_init(void) { #ifdef RT_USING_PIN rt_device_pin_register("gpio", &ops, RT_NULL); #endif /* install ISR */ rt_hw_interrupt_install(PIOD_INTERRUPT, gpio_irq_handler, &_g_gpio_irq_tbl[GPIO_PORT_D], "gpiod_irq"); rt_hw_interrupt_umask(PIOD_INTERRUPT); rt_hw_interrupt_install(PIOE_INTERRUPT, gpio_irq_handler, &_g_gpio_irq_tbl[GPIO_PORT_E], "gpioe_irq"); rt_hw_interrupt_umask(PIOE_INTERRUPT); rt_hw_interrupt_install(PIOF_INTERRUPT, gpio_irq_handler, &_g_gpio_irq_tbl[GPIO_PORT_F], "gpiof_irq"); rt_hw_interrupt_umask(PIOF_INTERRUPT); return 0; }
/** * This function will handle init uart */ void rt_hw_uart_init(void) { struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #if defined(RT_USING_UART0) #if(0) serial0.ops = &fh_uart_ops; serial0.config = config; /* register vcom device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STANDALONE, &uart0); rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, (void *)&(serial0.parent), "UART0"); rt_hw_interrupt_umask(uart0.irq); #endif serial0.ops = &fh_uart_ops; serial0.config = config; /* register vcom device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , &uart0); rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler, (void *)&(serial0.parent), "UART0"); rt_hw_interrupt_umask(uart0.irq); #endif #if defined(RT_USING_UART1) serial1.ops = &fh_uart_ops; serial1.config = config; /* register vcom device */ rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM , &uart1); rt_hw_interrupt_install(uart1.irq, rt_fh_uart_handler, (void *)&(serial1.parent), "UART1"); rt_hw_interrupt_umask(uart1.irq); #endif }
/** * This function will init pit for system ticks */ void rt_hw_timer_init() { at91sam926x_pit_init(); /* install interrupt handler */ rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, RT_NULL); rt_hw_interrupt_umask(AT91_ID_SYS); }
int rt_hw_gpio_init(void) { GPIO_DBG("Install gpio interrupt source...\n"); /* install ISR */ rt_hw_interrupt_install(IRQ_GPIO0,gpio_irq_handler,&_g_gpio_irq_tbl[GPIO_PORT_A],"GPIOAINT"); rt_hw_interrupt_umask(IRQ_GPIO0); rt_hw_interrupt_install(IRQ_GPIO1,gpio_irq_handler,&_g_gpio_irq_tbl[GPIO_PORT_B],"GPIOBINT"); rt_hw_interrupt_umask(IRQ_GPIO1); rt_hw_interrupt_install(IRQ_GPIO2,gpio_irq_handler,&_g_gpio_irq_tbl[GPIO_PORT_C],"GPIOCINT"); rt_hw_interrupt_umask(IRQ_GPIO2); rt_hw_interrupt_install(IRQ_GPIO3,gpio_irq_handler,&_g_gpio_irq_tbl[GPIO_PORT_D],"GPIODINT"); rt_hw_interrupt_umask(IRQ_GPIO3); return 0; }
/** * This function will handle init uart */ int rt_hw_uart_init(void) { asm_usart_gpio_init(); #if defined(RT_USING_UART0) Hw_UartInit(0); asm_serial_config_set_default(&serial0); /* register uart device */ rt_hw_serial_register(&serial0, "uart0", DRV_REG_OPS, &uart0); rt_hw_interrupt_install(uart0.irq, rt_asm_usart_handler, (void *)&(serial0.parent), "UART0"); rt_hw_interrupt_umask(uart0.irq); #endif #if defined(RT_USING_UART3) Hw_UartInit(3); asm_serial_config_set_default(&serial3); /* register uart device */ rt_hw_serial_register(&serial3, "uart3", DRV_REG_OPS, &uart3); rt_hw_interrupt_install(uart3.irq, rt_asm_usart_handler, (void *)&(serial3.parent), "UART3"); rt_hw_interrupt_umask(uart3.irq); #endif #if defined(RT_USING_UART4) Hw_UartInit(4); asm_serial_config_set_default(&serial4); /* register uart device */ rt_hw_serial_register(&serial4, "uart4", DRV_REG_OPS, &uart4); rt_hw_interrupt_install(uart4.irq, rt_asm_usart_handler, (void *)&(serial4.parent), "UART4"); rt_hw_interrupt_umask(uart4.irq); #endif return 0; }
/** * This function will init QEMU * */ void rt_hw_board_init(void) { /* initialize 8253 clock to interrupt 1000 times/sec */ outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) % 256); outb(IO_TIMER1, TIMER_DIV(RT_TICK_PER_SECOND) / 256); /* install interrupt handler */ rt_hw_interrupt_install(INTTIMER0, rt_timer_handler, RT_NULL, "tick"); rt_hw_interrupt_umask(INTTIMER0); #ifdef RT_USING_HOOK rt_thread_idle_sethook(idle_hook); #endif }
/** * This function will init LPC2478 board */ void rt_hw_board_init() { /* init console for rt_kprintf function */ rt_hw_console_init(); T0IR = 0xff; T0TC = 0; T0MCR = 0x03; T0MR0 = (DATA_COUNT); rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL); rt_hw_interrupt_umask(TIMER0_INT); T0TCR = 0x01; //enable timer0 counter }
/** * This function will init LPC2478 board */ void rt_hw_board_init() { #if defined(RT_USING_DEVICE) && defined(RT_USING_UART1) rt_hw_serial_init(); rt_console_set_device("uart1"); #endif T0IR = 0xff; T0TC = 0; T0MCR = 0x03; T0MR0 = (DATA_COUNT); rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick"); rt_hw_interrupt_umask(TIMER0_INT); T0TCR = 0x01; //enable timer0 counter }
/** * This function will initial sam7x board. */ void rt_hw_board_init() { extern void rt_serial_init(void); /* init hardware console */ rt_hw_console_init(); /* init led */ rt_hw_board_led_init(); /* init PITC */ AT91C_BASE_PITC->PITC_PIMR = (1 << 25) | (1 << 24) | PIV; /* install timer handler */ rt_hw_interrupt_install(AT91C_ID_SYS, rt_hw_timer_handler, RT_NULL, "tick"); AT91C_BASE_AIC->AIC_SMR[AT91C_ID_SYS] = 0; rt_hw_interrupt_umask(AT91C_ID_SYS); }
/* ----------------------- Start implementation -----------------------------*/ BOOL xMBPortTimersInit(USHORT usTim1Timerout50us) { /* all are interrupt mode,set Timer 3 MUX 1/4 */ TCFG1 &= 0xffff0fff; TCFG1 |= 0x00001000; TCNTB3 = (rt_int32_t)(usTim1Timerout50us*(PCLK/ (4 *16* 1000))) - 1; /* manual update */ TCON = TCON & (~(0x0f<<16)) | (0x02<<16); /* install interrupt handler */ rt_hw_interrupt_install(INTTIMER3, prvvTIMERExpiredISR, RT_NULL); rt_hw_interrupt_umask(INTTIMER3); /* start timer3, reload */ TCON = TCON & (~(0x0f<<16)) | (0x09<<16); return TRUE; }
/* init timer4 for system tick */ void timer_init(void) { gpio.GPFDAT = 0xff; /* turn off leds */ gpio.GPFCON &= ~0x33; /* key int */ gpio.GPFCON |= 0x22; TCFG0 = 99; TCFG1 = 0x03; /* PCLK/100/16 */ TCNTB0 = (int)(pclk/100/16/RT_TICK_PER_SECOND) - 1; /* one second */ TCON |= (1<<1); /* update count buf */ rt_hw_interrupt_install(10, rt_timer_handler, RT_NULL, "tick"); rt_hw_interrupt_umask(10); TCON = 0x09; /* set interval mode & run */ }
static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag) { unsigned int dsintr; enable_mdi(); mask_irq(28); sep_emac_write(MAC_INTMASK,0x0); //首先屏蔽中断 sepether_start(); /* Enable PHY interrupt */ *(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ; //1 stands for in *(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ; //for common use *(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080; //中断输入方式 *(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14); //中断类型为低电平解发 *(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080; //清除中断 *(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000; //清除中断 rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL); enable_irq(INTSRC_EXINT7); read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr); dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr); update_link_speed(dm9161_device.phy_addr); /************************************************************************************/ /* Enable MAC interrupts */ sep_emac_write(MAC_INTMASK,0xff); //open中断 sep_emac_write(MAC_INTSRC,0xff); //clear all mac irq unmask_irq(28); disable_mdi(); rt_kprintf("SEP4020 ethernet interface open!\n\r"); return RT_EOK; }
void rt_hw_serial_init(void) { volatile rt_uint8_t val; struct rt_ppc405_serial* device; device = (struct rt_ppc405_serial*) &ppc405_serial; device->parent.type = RT_Device_Class_Char; device->hw_base = UART0_BASE; device->baudrate = 115200; device->irqno = VECNUM_U0; rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */ rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); device->read_index = device->save_index = 0; out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ /* setup baudrate */ rt_serial_set_baudrate(device); out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ device->parent.type = RT_Device_Class_Char; device->parent.init = rt_serial_init; device->parent.open = rt_serial_open; device->parent.close = rt_serial_close; device->parent.read = rt_serial_read; device->parent.write = rt_serial_write; device->parent.control = rt_serial_control; device->parent.user_data = RT_NULL; rt_device_register(&device->parent, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); }
int rt_hw_timer_init(void) { uint32_t freq; // The ARM private peripheral clock is half the CPU clock. uint32_t periphClock = get_main_clock(CPU_CLK) / 2; uint32_t prescaler = (periphClock / 1000000) - 1; // Divide down the prescaler until it fits into 8 bits. We add up the number of ticks // it takes to equal a microsecond interval. while (prescaler > 0xff) { prescaler /= 2; } // Make sure the timer is off. HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 0; // Clear counter. HW_ARMGLOBALTIMER_COUNTERn_WR(0, 0); HW_ARMGLOBALTIMER_COUNTERn_WR(1, 0); // Set prescaler and clear other flags. HW_ARMGLOBALTIMER_CONTROL_WR(BF_ARMGLOBALTIMER_CONTROL_PRESCALER(prescaler)); // Now turn on the timer. HW_ARMGLOBALTIMER_CONTROL.B.TIMER_ENABLE = 1; freq = get_main_clock(IPG_CLK); epit_init(HW_EPIT1, CLKSRC_IPG_CLK, freq / 1000000, SET_AND_FORGET, 10000, WAIT_MODE_EN | STOP_MODE_EN); epit_counter_enable(HW_EPIT1, 10000, IRQ_MODE); rt_hw_interrupt_install(IMX_INT_EPIT1, rt_hw_timer_isr, RT_NULL, "tick"); rt_hw_interrupt_umask(IMX_INT_EPIT1); return 0; }
static rt_err_t eth_init(rt_device_t device ) { struct eth_device *eth_device = (struct eth_device *)device; RT_ASSERT(eth_device != RT_NULL); s32 ijk; s32 status = 0; u64 dma_addr; u32 Mac_changed = 0; struct pbuf *pbuf; u8 macaddr[6] = DEFAULT_MAC_ADDRESS; struct rt_eth_dev *dev = ð_dev; struct synopGMACNetworkAdapter *adapter = dev->priv; synopGMACdevice * gmacdev = (synopGMACdevice *)adapter->synopGMACdev; synopGMAC_reset(gmacdev); synopGMAC_attach(gmacdev,(regbase + MACBASE),(regbase + DMABASE), DEFAULT_PHY_BASE, macaddr); synopGMAC_read_version(gmacdev); synopGMAC_set_mdc_clk_div(gmacdev,GmiiCsrClk3); gmacdev->ClockDivMdc = synopGMAC_get_mdc_clk_div(gmacdev); init_phy(adapter->synopGMACdev); rt_kprintf("tx desc_queue\n"); synopGMAC_setup_tx_desc_queue(gmacdev,TRANSMIT_DESC_SIZE, RINGMODE); synopGMAC_init_tx_desc_base(gmacdev); rt_kprintf("rx desc_queue\n"); synopGMAC_setup_rx_desc_queue(gmacdev,RECEIVE_DESC_SIZE, RINGMODE); synopGMAC_init_rx_desc_base(gmacdev); DEBUG_MES("DmaRxBaseAddr = %08x\n",synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr)); // u32 dmaRx_Base_addr = synopGMACReadReg(gmacdev->DmaBase,DmaRxBaseAddr); // rt_kprintf("first_desc_addr = 0x%x\n", dmaRx_Base_addr); #ifdef ENH_DESC_8W synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength32 | DmaDescriptorSkip2 | DmaDescriptor8Words ); #else //synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip1); synopGMAC_dma_bus_mode_init(gmacdev, DmaBurstLength4 | DmaDescriptorSkip2); #endif synopGMAC_dma_control_init(gmacdev,DmaStoreAndForward |DmaTxSecondFrame|DmaRxThreshCtrl128); status = synopGMAC_check_phy_init(adapter); synopGMAC_mac_init(gmacdev); synopGMAC_pause_control(gmacdev); #ifdef IPC_OFFLOAD synopGMAC_enable_rx_chksum_offload(gmacdev); synopGMAC_rx_tcpip_chksum_drop_enable(gmacdev); #endif u32 skb; do{ skb = (u32)plat_alloc_memory(RX_BUF_SIZE); //should skb aligned here? if(skb == RT_NULL){ rt_kprintf("ERROR in skb buffer allocation\n"); break; } dma_addr = plat_dma_map_single(gmacdev,(void *)skb,RX_BUF_SIZE); //获取 skb 的 dma 地址 status = synopGMAC_set_rx_qptr(gmacdev,dma_addr,RX_BUF_SIZE,(u32)skb,0,0,0); if(status < 0) { rt_kprintf("status < 0!!\n"); plat_free_memory((void *)skb); } }while(status >= 0 && (status < (RECEIVE_DESC_SIZE - 1))); synopGMAC_clear_interrupt(gmacdev); synopGMAC_disable_mmc_tx_interrupt(gmacdev, 0xFFFFFFFF); synopGMAC_disable_mmc_rx_interrupt(gmacdev, 0xFFFFFFFF); synopGMAC_disable_mmc_ipc_rx_interrupt(gmacdev, 0xFFFFFFFF); // synopGMAC_disable_interrupt_all(gmacdev); synopGMAC_enable_interrupt(gmacdev, DmaIntEnable); synopGMAC_enable_dma_rx(gmacdev); synopGMAC_enable_dma_tx(gmacdev); plat_delay(DEFAULT_LOOP_VARIABLE); synopGMAC_check_phy_init(adapter); synopGMAC_mac_init(gmacdev); rt_timer_init(&dev->link_timer, "link_timer", synopGMAC_linux_cable_unplug_function, (void *)adapter, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); rt_timer_start(&dev->link_timer); #ifdef RT_USING_GMAC_INT_MODE /* installl isr */ DEBUG_MES("%s\n", __FUNCTION__); rt_hw_interrupt_install(LS1C_MAC_IRQ, eth_rx_irq, RT_NULL, "e0_isr"); rt_hw_interrupt_umask(LS1C_MAC_IRQ); #else rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer", eth_rx_irq, (void *)adapter, 1, RT_TIMER_FLAG_PERIODIC); rt_timer_start(&dev->rx_poll_timer); #endif /*RT_USING_GMAC_INT_MODE*/ rt_kprintf("eth_inited!\n"); return RT_EOK; }
/** * This function will handle init uart */ void rt_hw_uart_init(void) { at91_usart_gpio_init(); #if defined(RT_USING_DBGU) serial_dbgu.ops = &at91_usart_ops; serial_dbgu.config.baud_rate = BAUD_RATE_115200; serial_dbgu.config.bit_order = BIT_ORDER_LSB; serial_dbgu.config.data_bits = DATA_BITS_8; serial_dbgu.config.parity = PARITY_NONE; serial_dbgu.config.stop_bits = STOP_BITS_1; serial_dbgu.config.invert = NRZ_NORMAL; serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial_dbgu, "dbgu", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &dbgu); #endif #if defined(RT_USING_UART0) serial0.ops = &at91_usart_ops; serial0.config.baud_rate = BAUD_RATE_115200; serial0.config.bit_order = BIT_ORDER_LSB; serial0.config.data_bits = DATA_BITS_8; serial0.config.parity = PARITY_NONE; serial0.config.stop_bits = STOP_BITS_1; serial0.config.invert = NRZ_NORMAL; serial0.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart0); rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler, (void *)&(serial0.parent), "UART0"); rt_hw_interrupt_umask(uart0.irq); #endif #if defined(RT_USING_UART1) serial1.ops = &at91_usart_ops; serial1.int_rx = &uart1_int_rx; serial1.config.baud_rate = BAUD_RATE_115200; serial1.config.bit_order = BIT_ORDER_LSB; serial1.config.data_bits = DATA_BITS_8; serial1.config.parity = PARITY_NONE; serial1.config.stop_bits = STOP_BITS_1; serial1.config.invert = NRZ_NORMAL; serial1.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart1); rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler, (void *)&(serial1.parent), "UART1"); rt_hw_interrupt_umask(uart1.irq); #endif #if defined(RT_USING_UART2) serial2.ops = &at91_usart_ops; serial2.config.baud_rate = BAUD_RATE_115200; serial2.config.bit_order = BIT_ORDER_LSB; serial2.config.data_bits = DATA_BITS_8; serial2.config.parity = PARITY_NONE; serial2.config.stop_bits = STOP_BITS_1; serial2.config.invert = NRZ_NORMAL; serial2.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart2); rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler, (void *)&(serial2.parent), "UART2"); rt_hw_interrupt_umask(uart2.irq); #endif #if defined(RT_USING_UART3) serial3.ops = &at91_usart_ops; serial3.config.baud_rate = BAUD_RATE_115200; serial3.config.bit_order = BIT_ORDER_LSB; serial3.config.data_bits = DATA_BITS_8; serial3.config.parity = PARITY_NONE; serial3.config.stop_bits = STOP_BITS_1; serial3.config.invert = NRZ_NORMAL; serial3.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart3); rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler, (void *)&(serial3.parent), "UART3"); rt_hw_interrupt_umask(uart3.irq); #endif }
/** * This function will handle init uart */ void rt_hw_uart_init(void) { rt_uint32_t cd; #ifdef USE_UART1 #define BAUDRATE 115200 //rt_uint32_t uart_rate; //at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB); at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); writel(AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS, AT91SAM9260_BASE_US1 + AT91_US_CR); writel( AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | AT91_US_CHRL_8 | AT91_US_PAR_NONE | AT91_US_NBSTOP_1 | AT91_US_CHMODE_NORMAL, AT91SAM9260_BASE_US1 + AT91_US_MR);//0x100108c0 //at91_sys_write(AT91_USART1 + AT91_US_MR, 0x000008c0);//0x100108c0 cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE; writel(cd, AT91SAM9260_BASE_US1 + AT91_US_BRGR); writel(AT91_US_RXEN | AT91_US_TXEN, AT91SAM9260_BASE_US1 + AT91_US_CR); writel(0x1, AT91SAM9260_BASE_US1 + AT91_US_IER); /* install interrupt handler */ rt_hw_interrupt_install(AT91SAM9260_ID_US1, rt_serial_handler, RT_NULL); rt_hw_interrupt_umask(AT91SAM9260_ID_US1); #endif #ifdef USE_UART3 #define BAUDRATE 115200 //rt_uint32_t uart_rate; at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3); at91_sys_write(AT91_PIOB+0x04, (1<<10)|(1<<11)); at91_sys_write(AT91_PIOB+0x70, (1<<10)|(1<<11)); writel(AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS, AT91SAM9260_BASE_US1 + AT91_US_CR); writel( AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | AT91_US_CHRL_8 | AT91_US_PAR_NONE | AT91_US_NBSTOP_1 | AT91_US_CHMODE_NORMAL, AT91SAM9260_BASE_US3 + AT91_US_MR); cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE; writel(cd, AT91SAM9260_BASE_US3 + AT91_US_BRGR); writel(AT91_US_RXEN | AT91_US_TXEN, AT91SAM9260_BASE_US3 + AT91_US_CR); writel(0x1, AT91SAM9260_BASE_US3 + AT91_US_IER); /* install interrupt handler */ rt_hw_interrupt_install(AT91SAM9260_ID_US3, rt_serial_handler, RT_NULL); rt_hw_interrupt_umask(AT91SAM9260_ID_US3); #endif #ifdef USE_DBGU #define BAUDRATE 115200 //rt_uint32_t cd; at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); at91_sys_write(AT91_DBGU + AT91_US_CR, AT91_US_RSTTX | AT91_US_RSTRX | AT91_US_RXDIS | AT91_US_TXDIS); at91_sys_write(AT91_DBGU + AT91_US_IDR, 0xffffffff); at91_sys_write(AT91_DBGU + AT91_US_MR, AT91_US_USMODE_NORMAL | AT91_US_PAR_NONE); cd = (clk_get_rate(clk_get("mck")) / 16 + BAUDRATE/2) / BAUDRATE; at91_sys_write(AT91_DBGU + AT91_US_BRGR, cd); at91_sys_write(AT91_DBGU + AT91_US_CR, AT91_US_RXEN | AT91_US_TXEN); at91_sys_read(AT91_DBGU + AT91_US_CSR); //read for clearing interrupt at91_sys_write(AT91_DBGU + AT91_US_IER, 0x1); #endif }
int rt_hw_serial_init(void) { struct serial_configure config; poweron_per_domain(); start_uart_clk(); config_pinmux(); #ifdef RT_USING_UART0 config.baud_rate = BAUD_RATE_115200; config.bit_order = BIT_ORDER_LSB; config.data_bits = DATA_BITS_8; config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; serial0.ops = &am33xx_uart_ops; serial0.config = config; /* enable RX interrupt */ UART_IER_REG(uart0.base) = 0x01; /* install ISR */ rt_hw_interrupt_install(uart0.irq, am33xx_uart_isr, &serial0, "uart0"); rt_hw_interrupt_control(uart0.irq, 0, 0); rt_hw_interrupt_mask(uart0.irq); /* register UART0 device */ rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart0); #endif #ifdef RT_USING_UART1 config.baud_rate = BAUD_RATE_115200; config.bit_order = BIT_ORDER_LSB; config.data_bits = DATA_BITS_8; config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; serial1.ops = &am33xx_uart_ops; serial1.config = config; /* enable RX interrupt */ UART_IER_REG(uart1.base) = 0x01; /* install ISR */ rt_hw_interrupt_install(uart1.irq, am33xx_uart_isr, &serial1, "uart1"); rt_hw_interrupt_control(uart1.irq, 0, 0); rt_hw_interrupt_mask(uart1.irq); /* register UART0 device */ rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart1); #endif #ifdef RT_USING_UART2 config.baud_rate = BAUD_RATE_115200; config.bit_order = BIT_ORDER_LSB; config.data_bits = DATA_BITS_8; config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; serial2.ops = &am33xx_uart_ops; serial2.config = config; /* enable RX interrupt */ UART_IER_REG(uart2.base) = 0x01; /* install ISR */ rt_hw_interrupt_install(uart2.irq, am33xx_uart_isr, &serial2, "uart2"); rt_hw_interrupt_control(uart2.irq, 0, 0); rt_hw_interrupt_mask(uart2.irq); /* register UART2 device */ rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart2); #endif #ifdef RT_USING_UART3 config.baud_rate = BAUD_RATE_115200; config.bit_order = BIT_ORDER_LSB; config.data_bits = DATA_BITS_8; config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; serial3.ops = &am33xx_uart_ops; serial3.config = config; /* enable RX interrupt */ UART_IER_REG(uart3.base) = 0x01; /* install ISR */ rt_hw_interrupt_install(uart3.irq, am33xx_uart_isr, &serial3, "uart3"); rt_hw_interrupt_control(uart3.irq, 0, 0); rt_hw_interrupt_mask(uart3.irq); /* register UART3 device */ rt_hw_serial_register(&serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart3); #endif #ifdef RT_USING_UART4 config.baud_rate = BAUD_RATE_115200; config.bit_order = BIT_ORDER_LSB; config.data_bits = DATA_BITS_8; config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; serial4.ops = &am33xx_gdb_ops; serial4.config = config; /* enable RX interrupt */ UART_IER_REG(uart4.base) = 0x00; /* install ISR */ rt_hw_interrupt_install(uart4.irq, am33xx_uart_isr, &serial4, "uart4"); rt_hw_interrupt_control(uart4.irq, 0, 0); rt_hw_interrupt_mask(uart4.irq); /* register UART4 device */ rt_hw_serial_register(&serial4, "uart4", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM, &uart4); #endif #ifdef RT_USING_UART5 config.baud_rate = BAUD_RATE_115200; config.bit_order = BIT_ORDER_LSB; config.data_bits = DATA_BITS_8; config.parity = PARITY_NONE; config.stop_bits = STOP_BITS_1; config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; serial5.ops = &am33xx_uart_ops; serial5.config = config; /* enable RX interrupt */ UART_IER_REG(uart5.base) = 0x01; /* install ISR */ rt_hw_interrupt_install(uart5.irq, am33xx_uart_isr, &serial5, "uart5"); rt_hw_interrupt_control(uart5.irq, 0, 0); rt_hw_interrupt_mask(uart5.irq); /* register UART4 device */ rt_hw_serial_register(&serial5, "uart5", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &uart5); #endif return 0; }
int rt_hw_mouse_init(void) { rt_uint8_t value; rt_uint32_t id; struct mouse_pl050_pdata_t *pdat; virtual_addr_t virt = MOUSE_ADDRESS; int irq = MOUSE_IRQ_NUM; id = (((read32(virt + 0xfec) & 0xff) << 24) | ((read32(virt + 0xfe8) & 0xff) << 16) | ((read32(virt + 0xfe4) & 0xff) << 8) | ((read32(virt + 0xfe0) & 0xff) << 0)); if(((id >> 12) & 0xff) != 0x41 || (id & 0xfff) != 0x050) { dbg_log(DBG_ERROR, "read id fail id:0x%08x\n", id); return RT_ERROR; } pdat = rt_malloc(sizeof(struct mouse_pl050_pdata_t)); if(!pdat) { dbg_log(DBG_ERROR, "malloc memory\n", id); return RT_ERROR; } rt_memset(pdat, 0, sizeof(struct mouse_pl050_pdata_t)); pdat->virt = virt; pdat->irq = irq; pdat->xmax = MOUSE_XMAX; pdat->ymax = MOUSE_YMAX; pdat->xpos = pdat->xmax / 2; pdat->ypos = pdat->ymax / 2; pdat->packet[0] = 0; pdat->packet[1] = 0; pdat->packet[2] = 0; pdat->packet[3] = 0; pdat->index = 0; pdat->obtn = 0; write8(pdat->virt + MOUSE_CLKDIV, 0); write8(pdat->virt + MOUSE_CR, (1 << 2)); kmi_write(pdat, 0xff); kmi_read(pdat, &value); kmi_write(pdat, 0xf3); kmi_write(pdat, 200); kmi_write(pdat, 0xf3); kmi_write(pdat, 100); kmi_write(pdat, 0xf3); kmi_write(pdat, 80); kmi_write(pdat, 0xf2); kmi_read(pdat, &value); kmi_read(pdat, &value); kmi_write(pdat, 0xf3); kmi_write(pdat, 100); kmi_write(pdat, 0xe8); kmi_write(pdat, 0x02); kmi_write(pdat, 0xe6); kmi_write(pdat, 0xf4); kmi_read(pdat, &value); kmi_read(pdat, &value); kmi_read(pdat, &value); kmi_read(pdat, &value); write8(pdat->virt + MOUSE_CR, (1 << 2) | (1 << 4)); rt_hw_interrupt_install(pdat->irq, mouse_pl050_interrupt, (void *)pdat, "mouse"); rt_hw_interrupt_umask(pdat->irq); return RT_EOK; }
int mpu6050_init() { /* ** Configures I2C to Master mode to generate start ** condition on I2C bus and to transmit data at a ** speed of 100khz */ SetupI2C(); rt_hw_interrupt_install(SYS_INT_I2C0INT, mpu6050_isr, NULL, "mpu6050"); rt_hw_interrupt_mask(SYS_INT_I2C0INT); int result = mpu_init(); if(!result) { rt_kprintf("mpu initialization complete......\n "); //mpu_set_sensor if(!mpu_set_sensors(INV_XYZ_GYRO | INV_XYZ_ACCEL)) rt_kprintf("mpu_set_sensor complete ......\n"); else rt_kprintf("mpu_set_sensor come across error ......\n"); if(!mpu_configure_fifo(INV_XYZ_GYRO | INV_XYZ_ACCEL)) //mpu_configure_fifo rt_kprintf("mpu_configure_fifo complete ......\n"); else rt_kprintf("mpu_configure_fifo come across error ......\n"); if(!mpu_set_sample_rate(DEFAULT_MPU_HZ)) //mpu_set_sample_rate rt_kprintf("mpu_set_sample_rate complete ......\n"); else rt_kprintf("mpu_set_sample_rate error ......\n"); if(!dmp_load_motion_driver_firmware()) //dmp_load_motion_driver_firmvare rt_kprintf("dmp_load_motion_driver_firmware complete ......\n"); else rt_kprintf("dmp_load_motion_driver_firmware come across error ......\n"); if(!dmp_set_orientation(inv_orientation_matrix_to_scalar(gyro_orientation))) //dmp_set_orientation rt_kprintf("dmp_set_orientation complete ......\n"); else rt_kprintf("dmp_set_orientation come across error ......\n"); if(!dmp_enable_feature(DMP_FEATURE_6X_LP_QUAT | DMP_FEATURE_TAP | DMP_FEATURE_ANDROID_ORIENT | DMP_FEATURE_SEND_RAW_ACCEL | DMP_FEATURE_SEND_CAL_GYRO | DMP_FEATURE_GYRO_CAL)) //dmp_enable_feature rt_kprintf("dmp_enable_feature complete ......\n"); else rt_kprintf("dmp_enable_feature come across error ......\n"); if(!dmp_set_fifo_rate(DEFAULT_MPU_HZ)) //dmp_set_fifo_rate rt_kprintf("dmp_set_fifo_rate complete ......\n"); else rt_kprintf("dmp_set_fifo_rate come across error ......\n"); run_self_test(); if(!mpu_set_dmp_state(1)) rt_kprintf("mpu_set_dmp_state complete ......\n"); else rt_kprintf("mpu_set_dmp_state come across error ......\n"); } while(1) { dmp_read_fifo(gyro, accel, quat, &sensor_timestamp, &sensors, &more); /* Gyro and accel data are written to the FIFO by the DMP in chip * frame and hardware units. This behavior is convenient because it * keeps the gyro and accel outputs of dmp_read_fifo and * mpu_read_fifo consistent. */ /* if (sensors & INV_XYZ_GYRO ) send_packet(PACKET_TYPE_GYRO, gyro); if (sensors & INV_XYZ_ACCEL) send_packet(PACKET_TYPE_ACCEL, accel); */ /* Unlike gyro and accel, quaternions are written to the FIFO in * the body frame, q30. The orientation is set by the scalar passed * to dmp_set_orientation during initialization. */ if (sensors & INV_WXYZ_QUAT ) { q0=quat[0] / q30; q1=quat[1] / q30; q2=quat[2] / q30; q3=quat[3] / q30; Pitch = asin(2 * q1 * q3 - 2 * q0* q2)* 57.3; // pitch Roll = atan2(2 * q2 * q3 + 2 * q0 * q1, -2 * q1 * q1 - 2 * q2* q2 + 1)* 57.3; // roll Yaw = atan2(2*(q1*q2 + q0*q3),q0*q0+q1*q1-q2*q2-q3*q3) * 57.3; // printf("Pitch=%.2f ,Roll=%.2f ,Yaw=%.2f \n",Pitch,Roll,Yaw); UART1_ReportIMU(Yaw*10, Pitch*10, Roll*10,0,0,0,100); delay_ms(10); } } return 0; }
/* keep compatible with platform SDK */ void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr) { rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown"); }