static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
* The 0 argument tells rtc_init not to
* update CMOS unless it is invalid.
* 1 tells rtc_init to always initialize the CMOS.
*/
rtc_init(0);
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n");
}
static void lpc_init(device_t dev)
{
u8 byte;
u32 dword;
device_t sm_dev;
/* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);
/* Initialize isa dma */
isa_dma_init();
/* Enable DMA transaction on the LPC bus */
byte = pci_read_config8(dev, 0x40);
byte |= (1 << 2);
pci_write_config8(dev, 0x40, byte);
/* Disable the timeout mechanism on LPC */
byte = pci_read_config8(dev, 0x48);
byte &= ~(1 << 7);
pci_write_config8(dev, 0x48, byte);
/* Disable LPC MSI Capability */
byte = pci_read_config8(dev, 0x78);
byte &= ~(1 << 1);
byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going
on on LPC, it holds PCI grant, so no LPC slave cycle can
interrupt and visit LPC. */
pci_write_config8(dev, 0x78, byte);
/* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */
/* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */
byte = pci_read_config8(dev, 0xBB);
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
* The 0 argument tells rtc_init not to
* update CMOS unless it is invalid.
* 1 tells rtc_init to always initialize the CMOS.
*/
rtc_init(0);
}
static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
/* SB Configure HPET base and enable bit */
//- hpetInit(sb_config, &(sb_config->BuildParameters));
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
* The 0 argument tells rtc_init not to
* update CMOS unless it is invalid.
* 1 tells rtc_init to always initialize the CMOS.
*/
rtc_init(0);
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
}
