void bsp_start( void )
{
rtems_isr_entry *monitors_vector_table;
int index;
monitors_vector_table = (rtems_isr_entry *)0; /* 135Bug Vectors are at 0 */
m68k_set_vbr( monitors_vector_table );
for ( index=2 ; index<=255 ; index++ )
M68Kvec[ index ] = monitors_vector_table[ 32 ];
M68Kvec[ 2 ] = monitors_vector_table[ 2 ]; /* bus error vector */
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
m68k_set_vbr( &M68Kvec );
pcc->int_base_vector = PCC_BASE_VECTOR; /* Set the PCC int vectors base */
(*(uint8_t*)0xfffe2001) = 0x08;
/* make VME access round-robin */
rtems_cache_enable_instruction();
rtems_cache_enable_data();
}
/*
* bsp_start
*
* This routine does the bulk of the system initialisation.
*/
void bsp_start(void)
{
/* cfinit invalidates cache and sets acr registers */
/*
* Enable the cache, we only need to enable the instruction cache as the
* 532x has a unified data and instruction cache.
*/
rtems_cache_enable_instruction();
}
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
rtems_isr_entry *monitors_vector_table;
int index;
monitors_vector_table = (rtems_isr_entry *)0; /* 135Bug Vectors are at 0 */
m68k_set_vbr( monitors_vector_table );
for ( index=2 ; index<=255 ; index++ )
M68Kvec[ index ] = monitors_vector_table[ 32 ];
M68Kvec[ 2 ] = monitors_vector_table[ 2 ]; /* bus error vector */
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
m68k_set_vbr( &M68Kvec );
(*(uint8_t*)0xfffb0067) = 0x7f; /* make VME access round-robin */
rtems_cache_enable_instruction();
}
void bsp_start( void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/* Basic CPU initialization */
cpu_init();
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if INSTRUCTION_CACHE_ENABLE
rtems_cache_enable_instruction();
#endif
#if DATA_CACHE_ENABLE
rtems_cache_enable_data();
#endif
/*
* This is evaluated during runtime, so it should be ok to set it
* before we initialize the drivers.
*/
/* Initialize some device driver parameters */
/*
* get the (internal) bus frequency
* NOTE: the external bus may be clocked at a lower speed
* but this does not concern the internal units like PIT,
* DEC, baudrate generator etc)
*/
if (RTEMS_SUCCESSFUL !=
bsp_tqm_get_cib_uint32("cu",
&BSP_bus_frequency)) {
BSP_panic("Cannot determine BUS frequency\n");
}
bsp_clicks_per_usec = BSP_bus_frequency/1000000/16;
bsp_timer_least_valid = 3;
bsp_timer_average_overhead = 3;
/* Initialize exception handler */
sc = ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
interrupt_stack_start,
interrupt_stack_size
);
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot initialize exceptions");
}
/* Initalize interrupt support */
sc = bsp_interrupt_initialize();
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot intitialize interrupts");
}
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
void bsp_start( void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
unsigned long i = 0;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
get_ppc_cpu_type();
get_ppc_cpu_revision();
/* Basic CPU initialization */
cpu_init();
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#ifdef BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#ifdef BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
/*
* This is evaluated during runtime, so it should be ok to set it
* before we initialize the drivers.
*/
/* Initialize some device driver parameters */
#ifdef HAS_UBOOT
BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
#else /* HAS_UBOOT */
BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
#endif /* HAS_UBOOT */
bsp_time_base_frequency = BSP_bus_frequency / 4;
bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
rtems_counter_initialize_converter(bsp_time_base_frequency);
/* Initialize some console parameters */
for (i = 0; i < console_device_count; ++i) {
ns16550_context *ctx = (ns16550_context *) console_device_table[i].context;
ctx->clock = BSP_bus_frequency;
#ifdef HAS_UBOOT
ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
#endif
}
/* Initialize exception handler */
#ifndef BSP_DATA_CACHE_ENABLED
ppc_exc_cache_wb_check = 0;
#endif
ppc_exc_initialize(
(uintptr_t) bsp_section_work_begin,
rtems_configuration_get_interrupt_stack_size()
);
/* Install default handler for the decrementer exception */
sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
if (sc != RTEMS_SUCCESSFUL) {
rtems_panic("cannot install decrementer exception handler");
}
/* Initalize interrupt support */
bsp_interrupt_initialize();
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
/*
* bsp_start()
*
* Board-specific initialization code. Called from the generic boot_card()
* function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
* does some of the board independent initialization. It is called from the
* MBX8xx entry point _start() defined in
* rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
*
* _start() has set up a stack, has zeroed the .bss section, has turned off
* interrupts, and placed the processor in the supervisor mode. boot_card()
* has left the processor in that state when bsp_start() was called.
*
* RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF!
* ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL
* ADDRESSES. Software-controlled address translation would be required
* otherwise.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values: NONE
*/
void bsp_start(void)
{
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
mmu_init();
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if NVRAM_CONFIGURE == 1
if ( nvram->cache_mode & 0x02 )
rtems_cache_enable_instruction();
if ( nvram->cache_mode & 0x01 )
rtems_cache_enable_data();
#else
#if BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#if BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
#endif
/* Initialize exception handler */
ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) IntrStack_start,
(uintptr_t) intrStack - (uintptr_t) IntrStack_start
);
/* Initalize interrupt support */
bsp_interrupt_initialize();
/*
* initialize the device driver parameters
*/
#if ( defined(mbx860_001b) || \
defined(mbx860_002b) || \
defined(mbx860_003b) || \
defined(mbx860_003b) || \
defined(mbx860_004b) || \
defined(mbx860_005b) || \
defined(mbx860_006b) || \
defined(mbx821_001b) || \
defined(mbx821_002b) || \
defined(mbx821_003b) || \
defined(mbx821_004b) || \
defined(mbx821_005b) || \
defined(mbx821_006b))
bsp_clicks_per_usec = 0; /* for 32768Hz extclk */
#else
bsp_clicks_per_usec = 1; /* for 4MHz extclk */
#endif
bsp_serial_per_sec = 10000000;
bsp_serial_external_clock = true;
bsp_serial_xon_xoff = false;
bsp_serial_cts_rts = true;
bsp_serial_rate = 9600;
#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
bsp_clock_speed = 50000000;
bsp_timer_average_overhead = 3;
bsp_timer_least_valid = 3;
#else
bsp_clock_speed = 40000000;
bsp_timer_average_overhead = 3;
bsp_timer_least_valid = 3;
#endif
m8xx.scc2.sccm=0;
m8xx.scc2p.rbase=0;
m8xx.scc2p.tbase=0;
m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 );
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
rtems_isr_entry *monitors_vector_table;
int index;
uint8_t node_number;
monitors_vector_table = (rtems_isr_entry *)0; /* 147Bug Vectors are at 0 */
m68k_set_vbr( monitors_vector_table );
for ( index=2 ; index<=255 ; index++ )
M68Kvec[ index ] = monitors_vector_table[ 32 ];
M68Kvec[ 2 ] = monitors_vector_table[ 2 ]; /* bus error vector */
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
m68k_set_vbr( &M68Kvec );
pcc->int_base_vector = PCC_BASE_VECTOR & 0xF0;
/* Set the PCC int vectors base */
/* VME shared memory configuration */
/* Only the first node shares its top 128k DRAM */
vme_lcsr->utility_interrupt_vector = VME_BASE_VECTOR & 0xF8;
/* Set VMEchip base interrupt vector */
vme_lcsr->utility_interrupt_mask |= 0x02;
/* Enable SIGLP interruption (see shm support) */
pcc->general_purpose_control &= 0x10;
/* Enable VME master interruptions */
if (vme_lcsr->system_controller & 0x01) {
/* the board is system controller */
vme_lcsr->system_controller = 0x08;
/* Make VME access round-robin */
}
#if defined(RTEMS_MULTIPROCESSING)
node_number = (uint8_t)
(rtems_configuration_get_user_multiprocessing_table()->node - 1) & 0xF;
#else
node_number = 1;
#endif
/* Get and store node ID, first node_number = 0 */
vme_gcsr->board_identification = node_number;
vme_lcsr->gcsr_base_address = node_number;
/* Setup the base address of this board's gcsr */
vme_lcsr->timer_configuration = 0x6a;
/* Enable VME time outs, maximum periods */
if (node_number == 0) {
pcc->slave_base_address = 0x01;
/* Set local DRAM base address on the VME bus to the DRAM size */
vme_lcsr->vme_bus_requester = 0x80;
while (! (vme_lcsr->vme_bus_requester & 0x40));
/* Get VMEbus mastership */
vme_lcsr->slave_address_modifier = 0xfb;
/* Share everything */
vme_lcsr->slave_configuration = 0x80;
/* Share local DRAM */
vme_lcsr->vme_bus_requester = 0x0;
/* release bus */
} else {
pcc->slave_base_address = 0;
/* Set local DRAM base address on the VME bus to 0 */
vme_lcsr->vme_bus_requester = 0x80;
while (! (vme_lcsr->vme_bus_requester & 0x40));
/* Get VMEbus mastership */
vme_lcsr->slave_address_modifier = 0x08;
/* Share only the short adress range */
vme_lcsr->slave_configuration = 0;
/* Don't share local DRAM */
vme_lcsr->vme_bus_requester = 0x0;
/* release bus */
}
vme_lcsr->master_address_modifier = 0;
/* Automatically set the address modifier */
vme_lcsr->master_configuration = 1;
/* Disable D32 transfers : they don't work on my VMEbus rack */
rtems_cache_enable_instruction();
rtems_cache_enable_data();
}
void bsp_start(void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
/* Set MPC8260ADS board LEDS and Uart enable lines */
_BSP_GPLED0_off();
_BSP_GPLED1_off();
_BSP_Uart1_enable();
_BSP_Uart2_enable();
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
cpu_init();
/*
mmu_init();
*/
/* Initialize exception handler */
/* FIXME: Interrupt stack begin and size */
sc = ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
(uintptr_t) IntrStack_start,
(uintptr_t) intrStack - (uintptr_t) IntrStack_start
);
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot intitialize exceptions");
}
/* Initalize interrupt support */
sc = bsp_interrupt_initialize();
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot intitialize interrupts");
}
/*
mmu_init();
*/
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if INSTRUCTION_CACHE_ENABLE
rtems_cache_enable_instruction();
#endif
#if DATA_CACHE_ENABLE
rtems_cache_enable_data();
#endif
/*
* initialize the device driver parameters
*/
bsp_clicks_per_usec = 10; /* for 40MHz extclk */
bsp_serial_per_sec = 40000000;
bsp_serial_external_clock = 0;
bsp_serial_xon_xoff = 0;
bsp_serial_cts_rts = 0;
bsp_serial_rate = 9600;
bsp_timer_average_overhead = 3;
bsp_timer_least_valid = 3;
bsp_clock_speed = 40000000;
#ifdef REV_0_2
/* set up some board specific registers */
m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */
m8260.siumcr |= 0x08000000;
#endif
/* use BRG1 to generate 32kHz timebase */
/*
m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0;
*/
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
void bsp_start( void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
unsigned long i = 0;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/* Basic CPU initialization */
cpu_init();
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#ifdef BSP_INSTRUCTION_CACHE_ENABLED
rtems_cache_enable_instruction();
#endif
#ifdef BSP_DATA_CACHE_ENABLED
rtems_cache_enable_data();
#endif
/*
* This is evaluated during runtime, so it should be ok to set it
* before we initialize the drivers.
*/
/* Initialize some device driver parameters */
#ifdef HAS_UBOOT
BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
#else /* HAS_UBOOT */
BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
#endif /* HAS_UBOOT */
bsp_time_base_frequency = BSP_bus_frequency / 4;
bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
/* Initialize some console parameters */
for (i = 0; i < Console_Configuration_Count; ++i) {
Console_Configuration_Ports [i].ulClock = BSP_bus_frequency;
#ifdef HAS_UBOOT
Console_Configuration_Ports [i].pDeviceParams =
(void *) bsp_uboot_board_info.bi_baudrate;
#endif
}
/* Initialize exception handler */
#ifndef BSP_DATA_CACHE_ENABLED
ppc_exc_cache_wb_check = 0;
#endif
sc = ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
interrupt_stack_start,
interrupt_stack_size
);
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot initialize exceptions");
}
/* Install default handler for the decrementer exception */
sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot install decrementer exception handler");
}
/* Initalize interrupt support */
sc = bsp_interrupt_initialize();
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic("cannot intitialize interrupts\n");
}
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
void bsp_start(void)
{
extern void *_WorkspaceBase;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
register unsigned char* intrStack;
/* Set MPC8260ADS board LEDS and Uart enable lines */
_BSP_GPLED0_off();
_BSP_GPLED1_off();
_BSP_Uart1_enable();
_BSP_Uart2_enable();
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
cpu_init();
/*
mmu_init();
*/
/*
* Initialize some SPRG registers related to irq handling
*/
intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
_write_SPRG1((unsigned int)intrStack);
/* signal that we have fixed PR288 - eventually, this should go away */
_write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
/*
printk( "About to call initialize_exceptions\n" );
*/
/*
* Install our own set of exception vectors
*/
initialize_exceptions();
/*
mmu_init();
*/
/*
* Enable instruction and data caches. Do not force writethrough mode.
*/
#if INSTRUCTION_CACHE_ENABLE
rtems_cache_enable_instruction();
#endif
#if DATA_CACHE_ENABLE
rtems_cache_enable_data();
#endif
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
BSP_Configuration.work_space_start = (void *)&_WorkspaceBase;
/*
BSP_Configuration.microseconds_per_tick = 1000;
*/
/*
* initialize the CPU table for this BSP
*/
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.postdriver_hook = bsp_postdriver_hook;
if( Cpu_table.interrupt_stack_size < 4*1024 )
Cpu_table.interrupt_stack_size = 4 * 1024;
Cpu_table.clicks_per_usec = 10; /* for 40MHz extclk */
Cpu_table.serial_per_sec = 40000000;
Cpu_table.serial_external_clock = 0;
Cpu_table.serial_xon_xoff = 0;
Cpu_table.serial_cts_rts = 0;
Cpu_table.serial_rate = 9600;
Cpu_table.timer_average_overhead = 3;
Cpu_table.timer_least_valid = 3;
Cpu_table.clock_speed = 40000000;
#ifdef REV_0_2
/* set up some board specific registers */
m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */
m8260.siumcr |= 0x08000000;
#endif
/* use BRG1 to generate 32kHz timebase */
/*
m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0;
*/
/*
* Initalize RTEMS IRQ system
*/
BSP_rtems_irq_mng_init(0);
/*
* Call this in case we use TERMIOS for console I/O
*/
m8xx_uart_reserve_resources(&BSP_Configuration);
/*
rtems_termios_initialize();
*/
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif
}
