/*---------------------------------------------------------------------------*/
void
halTimer1Isr(void)
{
if(INT_TIM1FLAG & INT_TIMUIF) {
rtimer_clock_t now, clock_to_wait;
/* Overflow event. */
/* PRINTF("O %4x.\r\n", TIM1_CNT); */
/* printf("OV "); */
time_msb++;
now = ((rtimer_clock_t) time_msb << 16) | TIM1_CNT;
clock_to_wait = next_rtimer_time - now;
if(clock_to_wait <= 0x10000 && clock_to_wait > 0) {
/* We must now set the Timer Compare Register. */
TIM1_CCR1 = (uint16_t) clock_to_wait;
INT_TIM1FLAG = INT_TIMCC1IF;
INT_TIM1CFG |= INT_TIMCC1IF; /* Compare 1 interrupt enable. */
}
INT_TIM1FLAG = INT_TIMUIF;
} else {
if(INT_TIM1FLAG & INT_TIMCC1IF) {
/* Compare event. */
INT_TIM1CFG &= ~INT_TIMCC1IF; /* Disable the next compare interrupt */
PRINTF("\nCompare event %4x\r\n", TIM1_CNT);
PRINTF("INT_TIM1FLAG %2x\r\n", INT_TIM1FLAG);
ENERGEST_ON(ENERGEST_TYPE_IRQ);
rtimer_run_next();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
INT_TIM1FLAG = INT_TIMCC1IF;
}
}
}
void TC1_Handler(void)
{
volatile uint32_t ul_dummy;
/* Clear status bit to acknowledge interrupt */
ul_dummy = tc_get_status(TC0,1);
#if RTIMER_DEBUG
if ((ul_dummy & TC_SR_CPCS) == TC_SR_CPCS) {
#endif
tc_stop(TC0,1); // Crucial, since the execution may take long time
#if RTIMER_DEBUG
printf("Compare event %16x\r\n", ul_dummy);
#endif
tc_disable_interrupt(TC0,1,TC_IDR_CPCS); // Disable the next compare interrupt XXX XXX
ENERGEST_ON(ENERGEST_TYPE_IRQ);
rtimer_run_next(); /* Run the posted task. */
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
#if RTIMER_DEBUG
}
else {
printf("Unknown interrupt.\n\n");
}
#endif
}
void rtc_isr(void) {
PRINTF("rtc_wu_irq\n\r");
PRINTF("now is %u\n", rtimer_arch_now());
disable_rtc_wu();
disable_rtc_wu_irq();
rtimer_run_next();
clear_rtc_wu_evt();
}
/*---------------------------------------------------------------------------*/
void
rtimer_callback(void)
{
pic32_timer23_disable_irq();
TMR2 = schedule;
rtimer_run_next();
}
/*---------------------------------------------------------------------------*/
interrupt(TIMERA0_VECTOR) timera0 (void) {
ENERGEST_ON(ENERGEST_TYPE_IRQ);
rtimer_run_next();
if(process_nevents() > 0) {
LPM4_EXIT;
}
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/
void
RTC_IRQHandler(void)
{
RTC->IFC = RTC_IFC_COMP0;
RTC->IEN = 0x0000;
ENERGEST_ON(ENERGEST_TYPE_IRQ);
rtimer_run_next();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/
static void
rtc_compare_callback(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
rtc_count_disable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
rtimer_run_next();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
void
OSTIMER_IRQHandler(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
//clear RIT interrupt
LPC_RITIMER->CTRL |= 1;
NVIC_DisableIRQ(RIT_IRQn);
rtimer_run_next();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*--------------------------------------------------------------------------*/
ISR(TIMER0_A1, rtimer_a01_isr)
{
/* store the IV register as any read/write resets interrupt flags */
uint16_t ivreg = TA0IV;
if(ivreg & TA0IV_TACCR1) {
/* rtimer interrupt */
TA0CCTL1 &= ~CCIFG;
watchdog_start();
/* check for and run any pending rtimers */
rtimer_run_next();
/* also check for any pending events and wake up if needed */
if(process_nevents() > 0) {
LPM4_EXIT;
}
watchdog_stop();
} else if(ivreg & TA0IV_TACCR2) {
/* simple pwm interrupt */
TA0CCTL2 &= ~CCIFG;
if(spwm.on_time > 0) {
if(spwm.on_time == period) {
TA0CCTL2 &= ~CCIE; /* no need for interrupt, is at 100% DC */
/* SIMPLE_PWM_PORT(OUT) |= (1 << spwm.pin);*/
pwm_on_cb();
} else {
/* normal on-case */
if(period_end) {
period_end = 0;
TA0CCR2 = TAR + spwm.on_time;
/* SIMPLE_PWM_PORT(OUT) |= (1 << spwm.pin);*/
pwm_off_cb();
} else {
period_end = 1;
TA0CCR2 = TAR + (period - spwm.on_time);
/* SIMPLE_PWM_PORT(OUT) &= ~(1 << spwm.pin);*/
pwm_on_cb();
}
}
}
}
}
timera0 (void) {
ENERGEST_ON(ENERGEST_TYPE_IRQ);
watchdog_start();
rtimer_run_next();
if(process_nevents() > 0) {
LPM4_EXIT;
}
watchdog_stop();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/* The AON RTC interrupt handler */
void
cc26xx_rtc_isr(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if(ti_lib_aon_rtc_event_get(AON_RTC_CH0)) {
ti_lib_aon_rtc_event_clear(AON_RTC_CH0);
rtimer_run_next();
}
if(ti_lib_aon_rtc_event_get(AON_RTC_CH2)) {
ti_lib_aon_rtc_event_clear(AON_RTC_CH2);
clock_update();
}
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/** \brief Function for handling the TIMER1 interrupt.
* TIMER1 interrupt is triggered on COMPARE[0]. \n
* In this interrupt routine the rtimer count is incremented.
* If an rtimer task is scheduled then the interrupt is disabled and
* rtimer's next run function is called.
*/
void
TIMER0_IRQHandler ()
{
/* Check if this is a compare event and not an overflow */
if (NRF_TIMER0->EVENTS_COMPARE[0] == 1)
{
/* Reset the compare event */
NRF_TIMER0->EVENTS_COMPARE[0] = 0;
if (rtimer_scheduled)
{
NVIC_DisableIRQ (TIMER0_IRQn);
rtimer_scheduled = false;
rtimer_run_next ();
}
} /* else it is overflow */
else
printf("OVERFLOW\n\r");
}
/*---------------------------------------------------------------------------*/
void halTimer1Isr(void)
{
if(INT_TIM1FLAG & INT_TIMUIF) // Overflow event.
{
//PRINTF("O %4x.\r\n", TIM1_CNT);
//printf("OV ");
time_msb++;
rtimer_clock_t now = ((rtimer_clock_t)time_msb << 16)|TIM1_CNT;
rtimer_clock_t clock_to_wait = next_rtimer_time - now;
if(clock_to_wait <= 0x10000 && clock_to_wait > 0) // We must set now the Timer Compare Register.
{
TIM1_CCR1 = (int16u)clock_to_wait;
INT_TIM1FLAG = INT_TIMCC1IF;
INT_TIM1CFG |= INT_TIMCC1IF; // Compare 1 interrupt enable.
}
INT_TIM1FLAG = INT_TIMUIF;
}
else if(INT_TIM1FLAG & INT_TIMCC1IF) // Compare event.
{
INT_TIM1CFG &= ~INT_TIMCC1IF; // Disable the next compare interrupt
PRINTF("\nCompare event %4x\r\n", TIM1_CNT);
PRINTF("INT_TIM1FLAG %2x\r\n", INT_TIM1FLAG);
ENERGEST_ON(ENERGEST_TYPE_IRQ);
rtimer_run_next();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
INT_TIM1FLAG = INT_TIMCC1IF;
}
}
/*---------------------------------------------------------------------------*/
void
LPTMR_IRQHandler(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
watchdog_start();
PRINTF("rtimer_arch_init compare event at 0x%4x.\n", rtimer_arch_now());
LPTMR0_CMR = LPTMR_CMR_COMPARE(LPTMR_CMR_COMPARE_MASK);
LPTMR0_CSR = (uint32_t) ((LPTMR0_CSR
& (uint32_t) ~(uint32_t) (LPTMR_CSR_TIE_MASK))
| (uint32_t) (LPTMR_CSR_TCF_MASK)); // Clear interrupt flag and disable interrupt
rtimer_run_next();
watchdog_stop();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
void
TPM0_IRQHandler(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if (TPM_STATUS_CH0F_MASK & TPM0_STATUS)
{
/* disable tmp0 channel 0 interrupts */
TPM0_C0SC &= ~TPM_CnSC_CHIE_MASK;
}
/* Clear interrupt flags */
TPM0_STATUS = (TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK
| TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_CH4F_MASK
| TPM_STATUS_CH5F_MASK | TPM_STATUS_TOF_MASK);
rtimer_run_next();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
void RTC_IRQHandler(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
// Find reason of IRQ
if(RTC_IntGet() & RTC_IF_COMP0)
{
watchdog_start();
rtimer_run_next();
watchdog_stop();
// disable interrupt
RTC_IntDisable(RTC_IF_COMP0);
}
else
{
PRINTF("%s: unknown reason for RTC interrupt\r\n",__func__);
}
// Clear interrupts
RTC_IntClear(_RTC_IF_MASK);
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/
static void
interrupt(int sig)
{
signal(sig, interrupt);
rtimer_run_next();
}
