static int rtl8180_add_interface(struct ieee80211_hw *dev,
struct ieee80211_if_init_conf *conf)
{
struct rtl8180_priv *priv = dev->priv;
if (priv->mode != NL80211_IFTYPE_MONITOR)
return -EOPNOTSUPP;
switch (conf->type) {
case NL80211_IFTYPE_STATION:
priv->mode = conf->type;
break;
default:
return -EOPNOTSUPP;
}
priv->vif = conf->vif;
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
le32_to_cpu(*(__le32 *)conf->mac_addr));
rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
return 0;
}
static void rtl8180_stop(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
u8 reg;
int i;
priv->mode = NL80211_IFTYPE_UNSPECIFIED;
rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
reg = rtl818x_ioread8(priv, &priv->map->CMD);
reg &= ~RTL818X_CMD_TX_ENABLE;
reg &= ~RTL818X_CMD_RX_ENABLE;
rtl818x_iowrite8(priv, &priv->map->CMD, reg);
priv->rf->stop(dev);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
free_irq(priv->pdev->irq, dev);
rtl8180_free_rx_ring(dev);
for (i = 0; i < 4; i++)
rtl8180_free_tx_ring(dev, i);
}
/* Sets the MAC address of the card. */
static void rtl818x_set_hwaddr(struct net80211_device *dev, u8 *hwaddr)
{
struct rtl818x_priv *priv = dev->priv;
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
rtl818x_iowrite32(priv, (u32 *)&priv->map->MAC[0],
le32_to_cpu(*(u32 *)hwaddr));
rtl818x_iowrite16(priv, (u16 *)&priv->map->MAC[4],
le16_to_cpu(*(u16 *)(hwaddr + 4)));
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
}
void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
{
u8 reg;
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
rtl818x_iowrite8(priv, &priv->map->CONFIG3,
reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
rtl818x_iowrite8(priv, &priv->map->CONFIG3,
reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
}
static int rtl818x_config(struct net80211_device *dev, int changed)
{
struct rtl818x_priv *priv = dev->priv;
int i;
if (changed & NET80211_CFG_CHANNEL)
priv->rf->set_chan(dev, &dev->channels[dev->channel]);
if (changed & NET80211_CFG_ASSOC) {
for (i = 0; i < ETH_ALEN; i++)
rtl818x_iowrite8(priv, &priv->map->BSSID[i], dev->bssid[i]);
rtl818x_iowrite8(priv, &priv->map->MSR,
dev->state & NET80211_ASSOCIATED?
RTL818X_MSR_INFRA : RTL818X_MSR_NO_LINK);
}
if (changed & NET80211_CFG_PHY_PARAMS)
priv->rf->conf_erp(dev);
if (changed & NET80211_CFG_RATE) {
/* figure out the hardware rate number for the new
logical rate */
int hw_rate;
for (hw_rate = 0; hw_rate < RTL818X_NR_RATES &&
rtl818x_rates[hw_rate] != dev->rates[dev->rate];
hw_rate++)
;
if (hw_rate >= RTL818X_NR_RATES)
return -EINVAL;
priv->hw_rate = hw_rate;
/* and the RTS/CTS rate */
for (hw_rate = 0; hw_rate < RTL818X_NR_RATES &&
rtl818x_rates[hw_rate] !=
dev->rates[dev->rtscts_rate];
hw_rate++)
;
if (hw_rate >= RTL818X_NR_RATES)
hw_rate = priv->hw_rate;
priv->hw_rtscts_rate = hw_rate;
}
return 0;
}
static int rtl8180_config_interface(struct ieee80211_hw *dev,
struct ieee80211_vif *vif,
struct ieee80211_if_conf *conf)
{
struct rtl8180_priv *priv = dev->priv;
int i;
for (i = 0; i < ETH_ALEN; i++)
rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
if (is_valid_ether_addr(conf->bssid))
rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_INFRA);
else
rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_NO_LINK);
return 0;
}
static bool rtl8187_is_radio_enabled(struct rtl8187_priv *priv)
{
u8 gpio;
gpio = rtl818x_ioread8(priv, &priv->map->GPIO0);
rtl818x_iowrite8(priv, &priv->map->GPIO0, gpio & ~priv->rfkill_mask);
gpio = rtl818x_ioread8(priv, &priv->map->GPIO1);
return gpio & priv->rfkill_mask;
}
static int rtl818x_tx(struct net80211_device *dev, struct io_buffer *iob)
{
struct rtl818x_priv *priv = dev->priv;
struct rtl818x_tx_desc *entry;
u32 tx_flags;
u16 plcp_len = 0;
int len = iob_len(iob);
tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
RTL818X_TX_DESC_FLAG_LS | (priv->hw_rate << 24) | len;
if (priv->r8185) {
tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
RTL818X_TX_DESC_FLAG_NO_ENC;
} else {
unsigned int remainder;
plcp_len = DIV_ROUND_UP(16 * (len + 4),
(dev->rates[dev->rate] * 2) / 10);
remainder = (16 * (len + 4)) %
((dev->rates[dev->rate] * 2) / 10);
if (remainder > 0 && remainder <= 6)
plcp_len |= 1 << 15;
}
entry = &priv->tx_ring[priv->tx_prod];
if (dev->phy_flags & NET80211_PHY_USE_PROTECTION) {
tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
tx_flags |= priv->hw_rtscts_rate << 19;
entry->rts_duration = net80211_cts_duration(dev, len);
} else {
entry->rts_duration = 0;
}
if (entry->flags & RTL818X_TX_DESC_FLAG_OWN) {
/* card hasn't processed the old packet yet! */
return -EBUSY;
}
priv->tx_buf[priv->tx_prod] = iob;
priv->tx_prod = (priv->tx_prod + 1) % RTL818X_TX_RING_SIZE;
entry->plcp_len = cpu_to_le16(plcp_len);
entry->tx_buf = cpu_to_le32(virt_to_bus(iob->data));
entry->frame_len = cpu_to_le32(len);
entry->flags2 = /* alternate retry rate in 100kbps << 4 */ 0;
entry->retry_limit = RTL818X_MAX_RETRIES;
entry->flags = cpu_to_le32(tx_flags);
rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << 5));
return 0;
}
static void rtl818x_stop(struct net80211_device *dev)
{
struct rtl818x_priv *priv = dev->priv;
u8 reg;
rtl818x_irq(dev, 0);
reg = rtl818x_ioread8(priv, &priv->map->CMD);
reg &= ~RTL818X_CMD_TX_ENABLE;
reg &= ~RTL818X_CMD_RX_ENABLE;
rtl818x_iowrite8(priv, &priv->map->CMD, reg);
priv->rf->stop(dev);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
rtl818x_free_rx_ring(dev);
rtl818x_free_tx_ring(dev);
}
static void led_turn_off(struct work_struct *work)
{
/* As this routine does read/write operations on the hardware, it must
* be run from a work queue.
*/
u8 reg;
struct rtl8187_priv *priv = container_of(work, struct rtl8187_priv,
led_off.work);
struct rtl8187_led *led = &priv->led_tx;
/* Don't change the LED, when the device is down. */
if (!priv->vif || priv->vif->type == NL80211_IFTYPE_UNSPECIFIED)
return ;
/* Skip if the LED is not registered. */
if (!led->dev)
return;
mutex_lock(&priv->conf_mutex);
switch (led->ledpin) {
case LED_PIN_GPIO0:
rtl818x_iowrite8(priv, &priv->map->GPIO0, 0x01);
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0x01);
break;
case LED_PIN_LED0:
reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) | (1 << 4);
rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
break;
case LED_PIN_LED1:
reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) | (1 << 5);
rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
break;
case LED_PIN_HW:
default:
break;
}
mutex_unlock(&priv->conf_mutex);
}
static void rtl818x_spi_write_bit(struct bit_basher *basher,
unsigned int bit_id, unsigned long data)
{
struct rtl818x_priv *priv = container_of(basher, struct rtl818x_priv,
spibit.basher);
u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
u8 mask = rtl818x_eeprom_bits[bit_id];
reg = (reg & ~mask) | (data & mask);
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(10);
}
static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *info,
u32 changed)
{
struct rtl8180_priv *priv = dev->priv;
int i;
if (changed & BSS_CHANGED_BSSID) {
for (i = 0; i < ETH_ALEN; i++)
rtl818x_iowrite8(priv, &priv->map->BSSID[i],
info->bssid[i]);
if (is_valid_ether_addr(info->bssid))
rtl818x_iowrite8(priv, &priv->map->MSR,
RTL818X_MSR_INFRA);
else
rtl818x_iowrite8(priv, &priv->map->MSR,
RTL818X_MSR_NO_LINK);
}
if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
priv->rf->conf_erp(dev, info);
}
static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
{
struct ieee80211_hw *dev = eeprom->data;
struct rtl8180_priv *priv = dev->priv;
u8 reg = 2 << 6;
if (eeprom->reg_data_in)
reg |= RTL818X_EEPROM_CMD_WRITE;
if (eeprom->reg_data_out)
reg |= RTL818X_EEPROM_CMD_READ;
if (eeprom->reg_data_clock)
reg |= RTL818X_EEPROM_CMD_CK;
if (eeprom->reg_chip_select)
reg |= RTL818X_EEPROM_CMD_CS;
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(10);
}
static int __devinit rtl8180_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct ieee80211_hw *dev;
struct rtl8180_priv *priv;
unsigned long mem_addr, mem_len;
unsigned int io_addr, io_len;
int err, i;
struct eeprom_93cx6 eeprom;
const char *chip_name, *rf_name = NULL;
u32 reg;
u16 eeprom_val;
err = pci_enable_device(pdev);
if (err) {
printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
pci_name(pdev));
return err;
}
err = pci_request_regions(pdev, KBUILD_MODNAME);
if (err) {
printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
pci_name(pdev));
return err;
}
io_addr = pci_resource_start(pdev, 0);
io_len = pci_resource_len(pdev, 0);
mem_addr = pci_resource_start(pdev, 1);
mem_len = pci_resource_len(pdev, 1);
if (mem_len < sizeof(struct rtl818x_csr) ||
io_len < sizeof(struct rtl818x_csr)) {
printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
pci_name(pdev));
err = -ENOMEM;
goto err_free_reg;
}
if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) ||
(err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) {
printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
pci_name(pdev));
goto err_free_reg;
}
pci_set_master(pdev);
dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
if (!dev) {
printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
pci_name(pdev));
err = -ENOMEM;
goto err_free_reg;
}
priv = dev->priv;
priv->pdev = pdev;
dev->max_rates = 2;
SET_IEEE80211_DEV(dev, &pdev->dev);
pci_set_drvdata(pdev, dev);
priv->map = pci_iomap(pdev, 1, mem_len);
if (!priv->map)
priv->map = pci_iomap(pdev, 0, io_len);
if (!priv->map) {
printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
pci_name(pdev));
goto err_free_dev;
}
BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
priv->band.band = IEEE80211_BAND_2GHZ;
priv->band.channels = priv->channels;
priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
priv->band.bitrates = priv->rates;
priv->band.n_bitrates = 4;
dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
IEEE80211_HW_RX_INCLUDES_FCS |
IEEE80211_HW_SIGNAL_UNSPEC;
dev->queues = 1;
dev->max_signal = 65;
reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
reg &= RTL818X_TX_CONF_HWVER_MASK;
switch (reg) {
case RTL818X_TX_CONF_R8180_ABCD:
chip_name = "RTL8180";
break;
case RTL818X_TX_CONF_R8180_F:
chip_name = "RTL8180vF";
break;
case RTL818X_TX_CONF_R8185_ABC:
chip_name = "RTL8185";
break;
case RTL818X_TX_CONF_R8185_D:
chip_name = "RTL8185vD";
break;
default:
printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
pci_name(pdev), reg >> 25);
goto err_iounmap;
}
priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
if (priv->r8185) {
priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
pci_try_set_mwi(pdev);
}
eeprom.data = dev;
eeprom.register_read = rtl8180_eeprom_register_read;
eeprom.register_write = rtl8180_eeprom_register_write;
if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
eeprom.width = PCI_EEPROM_WIDTH_93C66;
else
eeprom.width = PCI_EEPROM_WIDTH_93C46;
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
udelay(10);
eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
eeprom_val &= 0xFF;
switch (eeprom_val) {
case 1: rf_name = "Intersil";
break;
case 2: rf_name = "RFMD";
break;
case 3: priv->rf = &sa2400_rf_ops;
break;
case 4: priv->rf = &max2820_rf_ops;
break;
case 5: priv->rf = &grf5101_rf_ops;
break;
case 9: priv->rf = rtl8180_detect_rf(dev);
break;
case 10:
rf_name = "RTL8255";
break;
default:
printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
pci_name(pdev), eeprom_val);
goto err_iounmap;
}
if (!priv->rf) {
printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
pci_name(pdev), rf_name);
goto err_iounmap;
}
eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
priv->csthreshold = eeprom_val >> 8;
if (!priv->r8185) {
__le32 anaparam;
eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
priv->anaparam = le32_to_cpu(anaparam);
eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
}
eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3);
if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
" randomly generated MAC addr\n", pci_name(pdev));
random_ether_addr(dev->wiphy->perm_addr);
}
/* CCK TX power */
for (i = 0; i < 14; i += 2) {
u16 txpwr;
eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
priv->channels[i].hw_value = txpwr & 0xFF;
priv->channels[i + 1].hw_value = txpwr >> 8;
}
/* OFDM TX power */
if (priv->r8185) {
for (i = 0; i < 14; i += 2) {
u16 txpwr;
eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
}
}
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
spin_lock_init(&priv->lock);
err = ieee80211_register_hw(dev);
if (err) {
printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
pci_name(pdev));
goto err_iounmap;
}
printk(KERN_INFO "%s: hwaddr %pM, %s + %s\n",
wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
chip_name, priv->rf->name);
return 0;
err_iounmap:
iounmap(priv->map);
err_free_dev:
pci_set_drvdata(pdev, NULL);
ieee80211_free_hw(dev);
err_free_reg:
pci_release_regions(pdev);
pci_disable_device(pdev);
return err;
}
static int rtl818x_start(struct net80211_device *dev)
{
struct rtl818x_priv *priv = dev->priv;
int ret;
u32 reg;
ret = rtl818x_init_rx_ring(dev);
if (ret)
return ret;
ret = rtl818x_init_tx_ring(dev);
if (ret)
goto err_free_rings;
ret = rtl818x_init_hw(dev);
if (ret)
goto err_free_rings;
rtl818x_set_hwaddr(dev, dev->netdev->ll_addr);
rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring_dma);
rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
reg = RTL818X_RX_CONF_ONLYERLPKT |
RTL818X_RX_CONF_RX_AUTORESETPHY |
RTL818X_RX_CONF_MGMT |
RTL818X_RX_CONF_DATA |
(7 << 8 /* MAX RX DMA */) |
RTL818X_RX_CONF_BROADCAST |
RTL818X_RX_CONF_NICMAC;
if (priv->r8185)
reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
else {
reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
? RTL818X_RX_CONF_CSDM1 : 0;
reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
? RTL818X_RX_CONF_CSDM2 : 0;
}
priv->rx_conf = reg;
rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
if (priv->r8185) {
reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
/* disable early TX */
rtl818x_iowrite8(priv, (u8 *)priv->map + 0xec, 0x3f);
}
reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
reg |= (6 << 21 /* MAX TX DMA */) |
RTL818X_TX_CONF_NO_ICV;
if (priv->r8185)
reg &= ~RTL818X_TX_CONF_PROBE_DTS;
else
reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
/* different meaning, same value on both rtl8185 and rtl8180 */
reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
reg = rtl818x_ioread8(priv, &priv->map->CMD);
reg |= RTL818X_CMD_RX_ENABLE;
reg |= RTL818X_CMD_TX_ENABLE;
rtl818x_iowrite8(priv, &priv->map->CMD, reg);
DBG("%s rtl818x: started\n", dev->netdev->name);
return 0;
err_free_rings:
rtl818x_free_rx_ring(dev);
if (priv->tx_ring)
rtl818x_free_tx_ring(dev);
DBG("%s rtl818x: failed to start\n", dev->netdev->name);
return ret;
}
static int rtl8180_start(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
int ret, i;
u32 reg;
ret = rtl8180_init_rx_ring(dev);
if (ret)
return ret;
for (i = 0; i < 4; i++)
if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
goto err_free_rings;
ret = rtl8180_init_hw(dev);
if (ret)
goto err_free_rings;
rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
ret = request_irq(priv->pdev->irq, &rtl8180_interrupt,
IRQF_SHARED, KBUILD_MODNAME, dev);
if (ret) {
printk(KERN_ERR "%s: failed to register IRQ handler\n",
wiphy_name(dev->wiphy));
goto err_free_rings;
}
rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
reg = RTL818X_RX_CONF_ONLYERLPKT |
RTL818X_RX_CONF_RX_AUTORESETPHY |
RTL818X_RX_CONF_MGMT |
RTL818X_RX_CONF_DATA |
(7 << 8 /* MAX RX DMA */) |
RTL818X_RX_CONF_BROADCAST |
RTL818X_RX_CONF_NICMAC;
if (priv->r8185)
reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
else {
reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
? RTL818X_RX_CONF_CSDM1 : 0;
reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
? RTL818X_RX_CONF_CSDM2 : 0;
}
priv->rx_conf = reg;
rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
if (priv->r8185) {
reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
/* disable early TX */
rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
}
reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
reg |= (6 << 21 /* MAX TX DMA */) |
RTL818X_TX_CONF_NO_ICV;
if (priv->r8185)
reg &= ~RTL818X_TX_CONF_PROBE_DTS;
else
reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
/* different meaning, same value on both rtl8185 and rtl8180 */
reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
reg = rtl818x_ioread8(priv, &priv->map->CMD);
reg |= RTL818X_CMD_RX_ENABLE;
reg |= RTL818X_CMD_TX_ENABLE;
rtl818x_iowrite8(priv, &priv->map->CMD, reg);
priv->mode = NL80211_IFTYPE_MONITOR;
return 0;
err_free_rings:
rtl8180_free_rx_ring(dev);
for (i = 0; i < 4; i++)
if (priv->tx_ring[i].desc)
rtl8180_free_tx_ring(dev, i);
return ret;
}
static int rtl8180_init_hw(struct ieee80211_hw *dev)
{
struct rtl8180_priv *priv = dev->priv;
u16 reg;
rtl818x_iowrite8(priv, &priv->map->CMD, 0);
rtl818x_ioread8(priv, &priv->map->CMD);
msleep(10);
/* reset */
rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
rtl818x_ioread8(priv, &priv->map->CMD);
reg = rtl818x_ioread8(priv, &priv->map->CMD);
reg &= (1 << 1);
reg |= RTL818X_CMD_RESET;
rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
rtl818x_ioread8(priv, &priv->map->CMD);
msleep(200);
/* check success of reset */
if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy));
return -ETIMEDOUT;
}
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
rtl818x_ioread8(priv, &priv->map->CMD);
msleep(200);
if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
/* For cardbus */
reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
reg |= 1 << 1;
rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
reg = rtl818x_ioread16(priv, &priv->map->FEMR);
reg |= (1 << 15) | (1 << 14) | (1 << 4);
rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
}
rtl818x_iowrite8(priv, &priv->map->MSR, 0);
if (!priv->r8185)
rtl8180_set_anaparam(priv, priv->anaparam);
rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
/* TODO: necessary? specs indicate not */
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
if (priv->r8185) {
reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
}
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
/* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
/* TODO: turn off hw wep on rtl8180 */
rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
if (priv->r8185) {
rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
/* TODO: set ClkRun enable? necessary? */
reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
} else {
rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
}
priv->rf->init(dev);
if (priv->r8185)
rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
return 0;
}
static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct rtl8180_priv *priv = dev->priv;
struct rtl8180_tx_ring *ring;
struct rtl8180_tx_desc *entry;
unsigned long flags;
unsigned int idx, prio;
dma_addr_t mapping;
u32 tx_flags;
u8 rc_flags;
u16 plcp_len = 0;
__le16 rts_duration = 0;
prio = skb_get_queue_mapping(skb);
ring = &priv->tx_ring[prio];
mapping = pci_map_single(priv->pdev, skb->data,
skb->len, PCI_DMA_TODEVICE);
tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
RTL818X_TX_DESC_FLAG_LS |
(ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
skb->len;
if (priv->r8185)
tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
RTL818X_TX_DESC_FLAG_NO_ENC;
rc_flags = info->control.rates[0].flags;
if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
} else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
}
if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
info);
if (!priv->r8185) {
unsigned int remainder;
plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
(ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
remainder = (16 * (skb->len + 4)) %
((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
if (remainder > 0 && remainder <= 6)
plcp_len |= 1 << 15;
}
spin_lock_irqsave(&priv->lock, flags);
idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
entry = &ring->desc[idx];
entry->rts_duration = rts_duration;
entry->plcp_len = cpu_to_le16(plcp_len);
entry->tx_buf = cpu_to_le32(mapping);
entry->frame_len = cpu_to_le32(skb->len);
entry->flags2 = info->control.rates[1].idx >= 0 ?
ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
entry->retry_limit = info->control.rates[0].count;
entry->flags = cpu_to_le32(tx_flags);
__skb_queue_tail(&ring->queue, skb);
if (ring->entries - skb_queue_len(&ring->queue) < 2)
ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
spin_unlock_irqrestore(&priv->lock, flags);
rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
return 0;
}
