/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
//u8 eRFPath;
//struct r8192_priv *priv = ieee80211_priv(dev);
//if (priv->card_8192 == NIC_8192SE)
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
//if (priv->card_8192_version >= VERSION_8192S_BCUT)
// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
//if (priv->card_8192_version >= VERSION_8192S_BCUT)
// rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
break;
}
}
// else
}
/*--------------------------------------------------------------------------
* Overview: set RF band width (20M or 40M)
* Input: struct net_device* dev
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
* Output: NONE
* Return: NONE
* Note: 8226 support both 20M and 40 MHz
*---------------------------------------------------------------------------*/
void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
u8 eRFPath;
struct r8192_priv *priv = ieee80211_priv(dev);
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
{
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
if(priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
{
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
//cosa add for sd3's request 01/23/2008
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
}
else
{
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
case HT_CHANNEL_WIDTH_20_40:
if(priv->card_8192_version == VERSION_819xU_A ||priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
{
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
//cosa add for sd3's request 01/23/2008
if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
else
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
}
else
{
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
default:
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
return;
}
void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
{
u8 eRFPath;
struct r8192_priv *priv = ieee80211_priv(dev);
if (1)
{
#ifndef RTL92SE_FPGA_VERIFY
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
#ifdef FIB_MODIFICATION
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
#endif
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
#ifdef FIB_MODIFICATION
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
#endif
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
break;
default:
;
break;
}
#endif
}
else
{
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
break;
case HT_CHANNEL_WIDTH_20_40:
break;
default:
;
break;
}
}
}
}
void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth)
{
u8 eRFPath;
struct r8192_priv *priv = rtllib_priv(dev);
if (IS_HARDWARE_TYPE_8192SE(dev))
{
#if (RTL92SE_FPGA_VERIFY == 0)
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
#if 1
priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
#else
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
#endif
break;
case HT_CHANNEL_WIDTH_20_40:
#if 1
priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff));
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
#else
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
#endif
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
break;
}
#endif
}
else
{
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
break;
case HT_CHANNEL_WIDTH_20_40:
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
}
}
//just in phy
void PHY_SetRF0222DBandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
u8 eRFPath;
struct r8192_priv *priv = ieee80211_priv(dev);
//if (IS_HARDWARE_TYPE_8192S(dev))
if (1)
{
#ifndef RTL92SE_FPGA_VERIFY
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
#ifdef FIB_MODIFICATION
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
#endif
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
#ifdef FIB_MODIFICATION
write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
#endif
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
break;
default:
;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
break;
}
#endif
}
else
{
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
//rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
//rtl8192_phy_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
break;
default:
;//RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
break;
}
}
}
}
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <*****@*****.**>
******************************************************************************/
// ****************************************************************************
//
// History:
// Data Who Remark
//
// 09/25/2008 MHC Create initial version.
// 11/05/2008 MHC Add API for tw power setting.
//
//
// ***************************************************************************/
#include "r8192U.h"
#include "r8192S_rtl6052.h"
#ifdef RTL8192SU
#include "r8192S_hw.h"
#include "r8192S_phyreg.h"
#include "r8192S_phy.h"
#else
#include "r8192U_hw.h"
#include "r819xU_phyreg.h"
#include "r819xU_phy.h"
#endif
//---------------------------Define Local Constant---------------------------*/
// Define local structure for debug!!!!!
typedef struct RF_Shadow_Compare_Map {
// Shadow register value
u32 Value;
// Compare or not flag
u8 Compare;
// Record If it had ever modified unpredicted
u8 ErrorOrNot;
// Recorver Flag
u8 Recorver;
//
u8 Driver_Write;
}RF_SHADOW_T;
//---------------------------Define Local Constant---------------------------*/
//------------------------Define global variable-----------------------------*/
//------------------------Define global variable-----------------------------*/
//---------------------Define local function prototype-----------------------*/
void phy_RF6052_Config_HardCode(struct net_device* dev);
RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev);
//---------------------Define local function prototype-----------------------*/
//------------------------Define function prototype--------------------------*/
extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate);
//------------------------Define function prototype--------------------------*/
//------------------------Define local variable------------------------------*/
// 2008/11/20 MH For Debug only, RF
static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM
//------------------------Define local variable------------------------------*/
//------------------------Define function prototype--------------------------*/
//-----------------------------------------------------------------------------
// Function: RF_ChangeTxPath
//
// Overview: For RL6052, we must change some RF settign for 1T or 2T.
//
// Input: u16 DataRate // 0x80-8f, 0x90-9f
//
// Output: NONE
//
// Return: NONE
//
// Revised History:
// When Who Remark
// 09/25/2008 MHC Create Version 0.
// Firmwaer support the utility later.
//
//---------------------------------------------------------------------------*/
extern void RF_ChangeTxPath(struct net_device* dev, u16 DataRate)
{
// We do not support gain table change inACUT now !!!! Delete later !!!
#if 0//(RTL92SE_FPGA_VERIFY == 0)
static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
static u4Byte tx_gain_tbl1[6]
= {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
static u4Byte tx_gain_tbl2[6]
= {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
u1Byte i;
if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x0f000);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G3, bMask20Bits, 0xeacf1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]);
// Set PA to high value
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x01e39);
}
else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
{
// Set TX SYNC power G2G3 loop filter
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x04440);
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G3, bMask20Bits, 0xea4f1);
// Change TX AGC gain table
for (i = 0; i < 6; i++)
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]);
// Set PA low gain
PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
RF_TXPA_G2, bMask20Bits, 0x01e19);
}
#endif
} // RF_ChangeTxPath */
//-----------------------------------------------------------------------------
// Function: PHY_RF6052SetBandwidth()
//
// Overview: This function is called by SetBWModeCallback8190Pci() only
//
// Input: PADAPTER Adapter
// WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
//
// Output: NONE
//
// Return: NONE
//
// Note: For RF type 0222D
//---------------------------------------------------------------------------*/
void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
struct r8192_priv *priv = rtllib_priv(dev);
#ifdef RTL8192SU //YJ,test,090113
//if (IS_HARDWARE_TYPE_8192S(dev))
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
break;
case HT_CHANNEL_WIDTH_20_40:
priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff));
rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
break;
}
}
// else
#else
u8 eRFPath;
{
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
//PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
//PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
}
#endif
}
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER dev
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
u8 eRFPath;
struct r8192_priv *priv = ieee80211_priv(dev);
if (IS_HARDWARE_TYPE_8192SE(dev))
{
#if (RTL92SE_FPGA_VERIFY == 0)
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
break;
}
#endif
}
else
{
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
//PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
break;
case HT_CHANNEL_WIDTH_20_40:
//PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
break;
default:
RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
}
}
void PHY_SetRF8256Bandwidth(struct net_device *dev,
enum ht_channel_width Bandwidth)
{
u8 eRFPath;
struct r8192_priv *priv = rtllib_priv(dev);
for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
if (priv->card_8192_version == VERSION_8190_BD ||
priv->card_8192_version == VERSION_8190_BE) {
rtl8192_phy_SetRFReg(dev,
(enum rf90_radio_path)eRFPath,
0x0b, bMask12Bits, 0x100);
rtl8192_phy_SetRFReg(dev,
(enum rf90_radio_path)eRFPath,
0x2c, bMask12Bits, 0x3d7);
rtl8192_phy_SetRFReg(dev,
(enum rf90_radio_path)eRFPath,
0x0e, bMask12Bits, 0x021);
} else {
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): "
"unknown hardware version\n");
}
break;
case HT_CHANNEL_WIDTH_20_40:
if (priv->card_8192_version == VERSION_8190_BD ||
priv->card_8192_version == VERSION_8190_BE) {
rtl8192_phy_SetRFReg(dev,
(enum rf90_radio_path)eRFPath,
0x0b, bMask12Bits, 0x300);
rtl8192_phy_SetRFReg(dev,
(enum rf90_radio_path)eRFPath,
0x2c, bMask12Bits, 0x3ff);
rtl8192_phy_SetRFReg(dev,
(enum rf90_radio_path)eRFPath,
0x0e, bMask12Bits, 0x0e1);
} else {
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): "
"unknown hardware version\n");
}
break;
default:
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown "
"Bandwidth: %#X\n", Bandwidth);
break;
}
}
return;
}
extern void PHY_RFShadowRecorver(
struct net_device * dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset)
{
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
{
if (RF_Shadow[eRFPath][Offset].Recorver == true)
{
rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bMask20Bits, RF_Shadow[eRFPath][Offset].Value);
RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x",
eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
}
}
} /* PHY_RFShadowRecorver */
extern void PHY_RFShadowRecorver(
struct net_device * dev,
RF90_RADIO_PATH_E eRFPath,
u32 Offset)
{
// Check if the address is error
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
{
// Check if we need to recorver the register.
if (RF_Shadow[eRFPath][Offset].Recorver == true)
{
rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value);
RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x",
eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
}
}
} /* PHY_RFShadowRecorver */
/*--------------------------------------------------------------------------
* Overview: set RF band width (20M or 40M)
* Input: struct net_device* dev
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
* Output: NONE
* Return: NONE
* Note: 8226 support both 20M and 40 MHz
*---------------------------------------------------------------------------*/
void PHY_SetRF8256Bandwidth(struct r8192_priv *priv, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
{
u8 eRFPath;
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
if (!rtl8192_phy_CheckIsLegalRFPath(priv, eRFPath))
continue;
switch(Bandwidth)
{
case HT_CHANNEL_WIDTH_20:
if(priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!
{
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
//cosa add for sd3's request 01/23/2008
//rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
}
else
{
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
case HT_CHANNEL_WIDTH_20_40:
if(priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE)// 8256 D-cut, E-cut, xiong: consider it later!
{
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);
rtl8192_phy_SetRFReg(priv, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);
}
else
{
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
default:
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
}
/*--------------------------------------------------------------------------
* Overview: Interface to config 8256
* Input: struct net_device* dev
* Output: NONE
* Return: NONE
*---------------------------------------------------------------------------*/
void phy_RF8256_Config_ParaFile(struct net_device* dev)
{
u32 u4RegValue = 0;
//static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
//static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
//static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C;
//static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
struct r8192_priv *priv = ieee80211_priv(dev);
u32 RegOffSetToBeCheck = 0x3;
u32 RegValueToBeCheck = 0x7f1;
u32 RF3_Final_Value = 0;
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
pPhyReg = &priv->PHYRegDef[eRFPath];
// Joseph test for shorten RF config
// pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
/*----Set RF_ENV output high----*/
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
/* Set bit number of Address and Data for RF register */
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
/*----Check RF block (for FPGA platform only)----*/
// TODO: this function should be removed on ASIC , Emily 2007.2.2
if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath))
{
RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
RetryTimes = ConstRetryTimes;
RF3_Final_Value = 0;
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_B:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_C:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_D:
while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
{
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(ret){
RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
}
RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
return ;
phy_RF8256_Config_ParaFile_Fail:
RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
return ;
}
bool phy_RF8256_Config_ParaFile(struct net_device *dev)
{
u32 u4RegValue = 0;
u8 eRFPath;
bool rtStatus = true;
struct bb_reg_definition *pPhyReg;
struct r8192_priv *priv = rtllib_priv(dev);
u32 RegOffSetToBeCheck = 0x3;
u32 RegValueToBeCheck = 0x7f1;
u32 RF3_Final_Value = 0;
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
eRFPath < priv->NumTotalRFPath; eRFPath++) {
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
pPhyReg = &priv->PHYRegDef[eRFPath];
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
bRFSI_RFENV);
break;
case RF90_PATH_B:
case RF90_PATH_D:
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
bRFSI_RFENV<<16);
break;
}
rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,
b3WireAddressLength, 0x0);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,
b3WireDataLength, 0x0);
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0,
bMask12Bits, 0xbf);
rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF,
(enum rf90_radio_path)eRFPath);
if (rtStatus != true) {
RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check "
"Radio[%d] Fail!!\n", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
RetryTimes = ConstRetryTimes;
RF3_Final_Value = 0;
switch (eRFPath) {
case RF90_PATH_A:
while (RF3_Final_Value != RegValueToBeCheck &&
RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
(enum rf90_radio_path)eRFPath,
RegOffSetToBeCheck,
bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final "
"value: %x\n", eRFPath,
RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_B:
while (RF3_Final_Value != RegValueToBeCheck &&
RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
(enum rf90_radio_path)eRFPath,
RegOffSetToBeCheck,
bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final "
"value: %x\n", eRFPath,
RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_C:
while (RF3_Final_Value != RegValueToBeCheck &&
RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
(enum rf90_radio_path)eRFPath,
RegOffSetToBeCheck,
bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final "
"value: %x\n", eRFPath,
RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_D:
while (RF3_Final_Value != RegValueToBeCheck &&
RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
(enum rf90_radio_path)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
(enum rf90_radio_path)eRFPath,
RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final "
"value: %x\n", eRFPath,
RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
}
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
u4RegValue);
break;
case RF90_PATH_B:
case RF90_PATH_D:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16,
u4RegValue);
break;
}
if (ret) {
RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():"
"Radio[%d] Fail!!", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
}
RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
return true;
phy_RF8256_Config_ParaFile_Fail:
RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
return false;
}
