static void _rtl92su_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
struct rtl_led *pLed0 = &(usbpriv->ledctl.sw_led0);
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
rtl92s_sw_led_on(hw, pLed0);
break;
case LED_CTL_POWER_OFF:
rtl92s_sw_led_off(hw, pLed0);
break;
default:
break;
}
}
/* taken from 8190n */
static int _rtl92su_macconfig_before_fwdownload3(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
unsigned int tries = 20;
u8 tmpu1b;
u16 tmpu2b;
/* Prevent EFUSE leakage */
rtl_write_byte(rtlpriv, REG_EFUSE_TEST + 3, 0xb0);
msleep(20);
rtl_write_byte(rtlpriv, REG_EFUSE_TEST + 3, 0x30);
/* Set control path switch to HW control and reset digital core,
* CPU core and MAC I/O core. */
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_CLKR);
if (tmpu2b & SYS_FWHW_SEL) {
tmpu2b &= ~(SYS_SWHW_SEL | SYS_FWHW_SEL);
/* Set failed, return to prevent hang. */
if (!rtl92s_halset_sysclk(hw, tmpu2b))
return -EIO;
}
/* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
tmpu1b &= 0x73;
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
/* wait for BIT 10/11/15 to pull high automatically!! */
mdelay(1);
rtl_write_byte(rtlpriv, REG_SPS0_CTRL + 1, 0x53);
rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x57);
/* Enable AFE Macro Block's Bandgap */
tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_MISC);
tmpu1b |= AFE_BGEN;
rtl_write_byte(rtlpriv, REG_AFE_MISC, tmpu1b);
mdelay(1);
/* Enable AFE Mbias */
tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_MISC);
tmpu1b |= AFE_BGEN | AFE_MBEN | AFE_MISC_I32_EN;
rtl_write_byte(rtlpriv, REG_AFE_MISC, tmpu1b);
mdelay(1);
/* Enable LDOA15 block */
tmpu1b = rtl_read_byte(rtlpriv, REG_LDOA15_CTRL);
tmpu1b |= LDA15_EN;
rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, tmpu1b);
/* Enable LDOV12D block */
tmpu1b = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
tmpu1b |= LDV12_EN;
rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, tmpu1b);
/* Set Digital Vdd to Retention isolation Path. */
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
tmpu2b |= ISO_PWC_DV2RP;
rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b);
/* For warm reboot NIC disappear bug.
* Also known as: Engineer Packet CP test Enable */
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
tmpu2b |= BIT(13);
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, tmpu2b);
/* Support 64k IMEM */
tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
tmpu1b &= 0x68;
rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tmpu1b);
/* Enable AFE clock source */
tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL);
tmpu1b |= BIT(0);
rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, tmpu1b);
/* Delay 1.5ms */
mdelay(2);
tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1);
tmpu1b &= ~BIT(2);
rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, tmpu1b);
/* Enable AFE PLL Macro Block *
* We need to delay 100u before enabling PLL. */
udelay(200);
tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
tmpu1b |= BIT(0) | BIT(4);
rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, tmpu1b);
/* for divider reset
* The clock will be stable with 500us delay after the PLL reset */
udelay(500);
rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b | BIT(0) |
BIT(4) | BIT(6)));
udelay(500);
rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
udelay(500);
/* Release isolation AFE PLL & MD */
tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
tmpu1b &= 0xee;
rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu1b);
/* Switch to 40MHz clock */
rtl_write_byte(rtlpriv, REG_SYS_CLKR, 0x00);
/* Disable CPU clock and 80MHz SSC to fix FW download timing issue */
tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
tmpu1b |= 0xa0;
rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmpu1b);
/* Enable MAC clock */
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_CLKR);
tmpu2b |= BIT(12) | SYS_MAC_CLK_EN;
rtl_write_word(rtlpriv, REG_SYS_CLKR, tmpu2b);
rtl_write_byte(rtlpriv, REG_PMC_FSM, 0x02);
/* Enable Core digital and enable IOREG R/W */
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
tmpu2b |= FEN_DCORE;
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, tmpu2b);
/* enable REG_EN */
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
tmpu2b |= FEN_MREGEN;
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, tmpu2b);
/* Switch the control path to FW */
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_CLKR);
tmpu2b |= SYS_FWHW_SEL;
tmpu2b &= ~SYS_SWHW_SEL;
rtl_write_word(rtlpriv, REG_SYS_CLKR, tmpu2b);
tmpu1b = rtl_read_byte(rtlpriv, REG_LD_RQPN);
tmpu1b |= BIT(6)|BIT(7);
tmpu1b |= BIT(5); /* Only for USBEP_FOUR */
rtl_write_byte(rtlpriv, REG_LD_RQPN, tmpu1b);
rtl_write_word(rtlpriv, REG_CR, HCI_TXDMA_EN |
HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | FW2HW_EN |
DDMA_EN | MACTXEN | MACRXEN | SCHEDULE_EN |
BB_GLB_RSTN | BBRSTN);
/* Fix USB RX FIFO error */
tmpu1b = rtl_read_byte(rtlpriv, REG_USB_AGG_TO);
tmpu1b |= BIT(7);
rtl_write_byte(rtlpriv, REG_USB_AGG_TO, tmpu1b);
/* Fix 8051 ROM incorrect code operation */
rtl_write_byte(rtlpriv, REG_USB_MAGIC, USB_MAGIC_BIT7);
/* To make sure that TxDMA can ready to download FW. */
/* We should reset TxDMA if IMEM RPT was not ready. */
do {
tmpu1b = rtl_read_byte(rtlpriv, REG_TCR);
if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
break;
msleep(20);
} while (--tries);
if (tries == 0) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
tmpu1b);
tmpu1b = rtl_read_byte(rtlpriv, REG_CR);
rtl_write_byte(rtlpriv, REG_CR, tmpu1b & (~TXDMA_EN));
msleep(20);
/* Reset TxDMA */
rtl_write_byte(rtlpriv, REG_CR, tmpu1b | TXDMA_EN);
}
/* After MACIO reset,we must refresh LED state. */
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS ||
ppsc->rfoff_reason == 0) {
enum rf_pwrstate rfpwr_state_toset;
struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
struct rtl_led *pLed0 = &(usbpriv->ledctl.sw_led0);
rfpwr_state_toset = rtl92s_rf_onoff_detect(hw);
if (rfpwr_state_toset == ERFON)
rtl92s_sw_led_on(hw, pLed0);
}
return 0;
}
