bool rtl92c_phy_bb_config(struct ieee80211_hw *hw) { bool rtstatus = true; struct rtl_priv *rtlpriv = rtl_priv(hw); u16 regval; u32 regvaldw; u8 reg_hwparafile = 1; _rtl92c_phy_init_bb_rf_register_definition(hw); regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) | BIT(0) | BIT(1)); rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB); rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); if (reg_hwparafile == 1) rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw); return rtstatus; }
void rtl92c_init_edca(struct ieee80211_hw *hw) { u16 value16; struct rtl_priv *rtlpriv = rtl_priv(hw); /* disable EDCCA count down, to reduce collison and retry */ value16 = rtl_read_word(rtlpriv, REG_RD_CTRL); value16 |= DIS_EDCA_CNT_DWN; rtl_write_word(rtlpriv, REG_RD_CTRL, value16); /* Update SIFS timing. ?????????? * pHalData->SifsTime = 0x0e0e0a0a; */ rtl92c_set_cck_sifs(hw, 0xa, 0xa); rtl92c_set_ofdm_sifs(hw, 0xe, 0xe); /* Set CCK/OFDM SIFS to be 10us. */ rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a); rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010); rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204); rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004); /* TXOP */ rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B); rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F); rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324); rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226); /* PIFS */ rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); /* AGGR BREAK TIME Register */ rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02); rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02); }
bool rtl92cu_phy_bb_config( struct ieee80211_hw *hw ) { bool rtstatus = true; struct rtl_priv *rtlpriv = rtl_priv( hw ); struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) ); u16 regval; u32 regval32; u8 b_reg_hwparafile = 1; _rtl92c_phy_init_bb_rf_register_definition( hw ); regval = rtl_read_word( rtlpriv, REG_SYS_FUNC_EN ); rtl_write_word( rtlpriv, REG_SYS_FUNC_EN, regval | BIT( 13 ) | BIT( 0 ) | BIT( 1 ) ); rtl_write_byte( rtlpriv, REG_AFE_PLL_CTRL, 0x83 ); rtl_write_byte( rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb ); rtl_write_byte( rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB ); if ( IS_HARDWARE_TYPE_8192CE( rtlhal ) ) { rtl_write_byte( rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB ); } else if ( IS_HARDWARE_TYPE_8192CU( rtlhal ) ) { rtl_write_byte( rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB ); } regval32 = rtl_read_dword( rtlpriv, 0x87c ); rtl_write_dword( rtlpriv, 0x87c, regval32 & ( ~BIT( 31 ) ) ); if ( IS_HARDWARE_TYPE_8192CU( rtlhal ) ) rtl_write_byte( rtlpriv, REG_LDOHCI12_CTRL, 0x0f ); rtl_write_byte( rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80 ); if ( b_reg_hwparafile == 1 ) rtstatus = _rtl92c_phy_bb8192c_config_parafile( hw ); return rtstatus; }
static bool _rtl92s_firmware_enable_cpu( struct ieee80211_hw *hw ) { struct rtl_priv *rtlpriv = rtl_priv( hw ); u32 ichecktime = 200; u16 tmpu2b; u8 tmpu1b, cpustatus = 0; _rtl92s_fw_set_rqpn( hw ); /* Enable CPU. */ tmpu1b = rtl_read_byte( rtlpriv, SYS_CLKR ); /* AFE source */ rtl_write_byte( rtlpriv, SYS_CLKR, ( tmpu1b | SYS_CPU_CLKSEL ) ); tmpu2b = rtl_read_word( rtlpriv, REG_SYS_FUNC_EN ); rtl_write_word( rtlpriv, REG_SYS_FUNC_EN, ( tmpu2b | FEN_CPUEN ) ); /* Polling IMEM Ready after CPU has refilled. */ do { cpustatus = rtl_read_byte( rtlpriv, TCR ); if ( cpustatus & IMEM_RDY ) { RT_TRACE( COMP_INIT, DBG_LOUD, ( "IMEM Ready after CPU has refilled.\n" ) ); break; } udelay( 100 ); } while ( ichecktime-- ); if ( !( cpustatus & IMEM_RDY ) ) return false; return true; }
static int _rtl92s_firmware_enable_cpu(struct ieee80211_hw *hw) { struct rtl_priv *rtlpriv = rtl_priv(hw); u32 ichecktime = 200; u16 tmpu2b; u8 tmpu1b, cpustatus = 0; /* select clock */ tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR); rtl_write_byte(rtlpriv, REG_SYS_CLKR, (tmpu1b | SYS_CPU_CLKSEL)); /* Enable CPU. */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | FEN_CPUEN)); /* Polling IMEM Ready after CPU has refilled. */ do { cpustatus = rtl_read_byte(rtlpriv, REG_TCR); if (cpustatus & IMEM_RDY) { RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "IMEM Ready after CPU has refilled\n"); break; } udelay(100); } while (ichecktime--); return !!(cpustatus & IMEM_RDY) ? 0 : -ETIMEDOUT; }
u16 halbtc_read_2byte(void *bt_context, u32 reg_addr) { struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context; struct rtl_priv *rtlpriv = btcoexist->adapter; return rtl_read_word(rtlpriv, reg_addr); }
bool rtl8822be_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index) { struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); struct rtl_priv *rtlpriv = rtl_priv(hw); bool ret = false; struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; u16 cur_tx_rp, cur_tx_wp; u16 tmp16; /* * design rule: * idx <= cur_tx_rp <= hw_rp <= cur_tx_wp = hw_wp */ if (index == ring->cur_tx_rp) { /* update only if sw_rp reach hw_rp */ tmp16 = rtl_read_word( rtlpriv, get_desc_address_from_queue_index(hw_queue) + 2); cur_tx_rp = tmp16 & 0x01ff; cur_tx_wp = ring->cur_tx_wp; /* don't need to update ring->cur_tx_wp */ ring->cur_tx_rp = cur_tx_rp; } if (index == ring->cur_tx_rp) ret = false; /* no more */ else ret = true; /* more */ if (hw_queue == BEACON_QUEUE) ret = true; if (rtlpriv->rtlhal.driver_is_goingto_unload || rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) ret = true; return ret; }
u16 rtl92c_get_data_filter(struct ieee80211_hw *hw) { struct rtl_priv *rtlpriv = rtl_priv(hw); return rtl_read_word(rtlpriv, REG_RXFLTMAP2); }
int rtl92su_hw_init(struct ieee80211_hw *hw) { struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); struct rtl_phy *rtlphy = &(rtlpriv->phy); struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); int err = 0; bool rtstatus = true; u8 i; int wdcapra_add[] = { REG_EDCA_BE_PARAM, REG_EDCA_BK_PARAM, REG_EDCA_VI_PARAM, REG_EDCA_VO_PARAM}; u8 secr_value = 0x0; /* 1. MAC Initialize */ /* Before FW download, we have to set some MAC register */ err = _rtl92su_macconfig_before_fwdownload(hw); if (err) { RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "Failed to get the device ready for the firmware (%d)\n", err); return err; } rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv, REG_PMC_FSM) >> 16) & 0xF); /* 2. download firmware */ rtstatus = rtl92s_download_fw(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "Failed to download FW. Init HW without FW now... Please copy FW into /lib/firmware/rtlwifi\n"); return -ENOENT; } /* After FW download, we have to reset MAC register */ _rtl92su_macconfig_after_fwdownload(hw); /*Retrieve default FW Cmd IO map. */ rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, REG_LBUS_MON_ADDR); rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, REG_LBUS_ADDR_MASK); /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */ rtstatus = rtl92s_phy_mac_config(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n"); return -EINVAL; } /* because last function modify RCR, so we update * rcr var here, or TP will unstable for receive_config * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 */ /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */ /* We must set flag avoid BB/RF config period later!! */ rtl_write_word(rtlpriv, CMDR, 0x37FC); /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */ rtstatus = rtl92s_phy_bb_config(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n"); return -ENODEV; } /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */ /* Before initalizing RF. We can not use FW to do RF-R/W. */ rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; /* Before RF-R/W we must execute the IO from Scott's suggestion. */ rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0xDB); if (rtlhal->version == VERSION_8192S_ACUT) rtl_write_byte(rtlpriv, REG_SPS1_CTRL + 3, 0x07); else rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07); rtstatus = rtl92s_phy_rf_config(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n"); return -EOPNOTSUPP; } /* After read predefined TXT, we must set BB/MAC/RF * register as our requirement */ rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, (enum radio_path)0, RF_CHNLBW, RFREG_OFFSET_MASK); rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw, (enum radio_path)1, RF_CHNLBW, RFREG_OFFSET_MASK); /*---- Set CCK and OFDM Block "ON"----*/ rtl_set_bbreg(hw, REG_RFPGA0_RFMOD, BCCKEN, 0x1); rtl_set_bbreg(hw, REG_RFPGA0_RFMOD, BOFDMEN, 0x1); /*3 Set Hardware(Do nothing now) */ _rtl92su_hw_configure(hw); /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ /* TX power index for different rate set. */ /* Get original hw reg values */ rtl92s_phy_get_hw_reg_originalvalue(hw); /* Write correct tx power index */ rtl92s_phy_set_txpower(hw, rtlphy->current_channel); /* We must set MAC address after firmware download. */ for (i = 0; i < 6; i++) rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); /* We enable high power and RA related mechanism after NIC * initialized. */ if (hal_get_firmwareversion(rtlpriv) >= 0x35) { /* Fw v.53 and later. */ rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT); } else if (hal_get_firmwareversion(rtlpriv) == 0x34) { /* Fw v.52. */ rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_INIT); rtl92s_phy_chk_fwcmd_iodone(hw); } else { /* Compatible earlier FW version. */ rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_RESET); rtl92s_phy_chk_fwcmd_iodone(hw); rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_ACTIVE); rtl92s_phy_chk_fwcmd_iodone(hw); rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_REFRESH); rtl92s_phy_chk_fwcmd_iodone(hw); } /* Security related * 1. Clear all H/W keys. * 2. Enable H/W encryption/decryption. */ rtl_cam_reset_all_entry(hw); secr_value |= SCR_TXENCENABLE; secr_value |= SCR_RXENCENABLE; secr_value |= SCR_NOSKMC; rtl_write_byte(rtlpriv, REG_SECR, secr_value); for (i = 0; i < 4; i++) rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); if (rtlphy->rf_type == RF_1T2R) { bool mrc2set = true; /* Turn on B-Path */ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set); } rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON); rtl92s_dm_init(hw); return err; }
/* taken from 8190n */ static int _rtl92su_macconfig_before_fwdownload3(struct ieee80211_hw *hw) { struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); unsigned int tries = 20; u8 tmpu1b; u16 tmpu2b; /* Prevent EFUSE leakage */ rtl_write_byte(rtlpriv, REG_EFUSE_TEST + 3, 0xb0); msleep(20); rtl_write_byte(rtlpriv, REG_EFUSE_TEST + 3, 0x30); /* Set control path switch to HW control and reset digital core, * CPU core and MAC I/O core. */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_CLKR); if (tmpu2b & SYS_FWHW_SEL) { tmpu2b &= ~(SYS_SWHW_SEL | SYS_FWHW_SEL); /* Set failed, return to prevent hang. */ if (!rtl92s_halset_sysclk(hw, tmpu2b)) return -EIO; } /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */ tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); tmpu1b &= 0x73; rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); /* wait for BIT 10/11/15 to pull high automatically!! */ mdelay(1); rtl_write_byte(rtlpriv, REG_SPS0_CTRL + 1, 0x53); rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x57); /* Enable AFE Macro Block's Bandgap */ tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_MISC); tmpu1b |= AFE_BGEN; rtl_write_byte(rtlpriv, REG_AFE_MISC, tmpu1b); mdelay(1); /* Enable AFE Mbias */ tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_MISC); tmpu1b |= AFE_BGEN | AFE_MBEN | AFE_MISC_I32_EN; rtl_write_byte(rtlpriv, REG_AFE_MISC, tmpu1b); mdelay(1); /* Enable LDOA15 block */ tmpu1b = rtl_read_byte(rtlpriv, REG_LDOA15_CTRL); tmpu1b |= LDA15_EN; rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, tmpu1b); /* Enable LDOV12D block */ tmpu1b = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); tmpu1b |= LDV12_EN; rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, tmpu1b); /* Set Digital Vdd to Retention isolation Path. */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); tmpu2b |= ISO_PWC_DV2RP; rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b); /* For warm reboot NIC disappear bug. * Also known as: Engineer Packet CP test Enable */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); tmpu2b |= BIT(13); rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, tmpu2b); /* Support 64k IMEM */ tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1); tmpu1b &= 0x68; rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tmpu1b); /* Enable AFE clock source */ tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL); tmpu1b |= BIT(0); rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, tmpu1b); /* Delay 1.5ms */ mdelay(2); tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1); tmpu1b &= ~BIT(2); rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, tmpu1b); /* Enable AFE PLL Macro Block * * We need to delay 100u before enabling PLL. */ udelay(200); tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL); tmpu1b |= BIT(0) | BIT(4); rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, tmpu1b); /* for divider reset * The clock will be stable with 500us delay after the PLL reset */ udelay(500); rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4) | BIT(6))); udelay(500); rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); udelay(500); /* Release isolation AFE PLL & MD */ tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); tmpu1b &= 0xee; rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu1b); /* Switch to 40MHz clock */ rtl_write_byte(rtlpriv, REG_SYS_CLKR, 0x00); /* Disable CPU clock and 80MHz SSC to fix FW download timing issue */ tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR); tmpu1b |= 0xa0; rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmpu1b); /* Enable MAC clock */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_CLKR); tmpu2b |= BIT(12) | SYS_MAC_CLK_EN; rtl_write_word(rtlpriv, REG_SYS_CLKR, tmpu2b); rtl_write_byte(rtlpriv, REG_PMC_FSM, 0x02); /* Enable Core digital and enable IOREG R/W */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); tmpu2b |= FEN_DCORE; rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, tmpu2b); /* enable REG_EN */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); tmpu2b |= FEN_MREGEN; rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, tmpu2b); /* Switch the control path to FW */ tmpu2b = rtl_read_word(rtlpriv, REG_SYS_CLKR); tmpu2b |= SYS_FWHW_SEL; tmpu2b &= ~SYS_SWHW_SEL; rtl_write_word(rtlpriv, REG_SYS_CLKR, tmpu2b); tmpu1b = rtl_read_byte(rtlpriv, REG_LD_RQPN); tmpu1b |= BIT(6)|BIT(7); tmpu1b |= BIT(5); /* Only for USBEP_FOUR */ rtl_write_byte(rtlpriv, REG_LD_RQPN, tmpu1b); rtl_write_word(rtlpriv, REG_CR, HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | FW2HW_EN | DDMA_EN | MACTXEN | MACRXEN | SCHEDULE_EN | BB_GLB_RSTN | BBRSTN); /* Fix USB RX FIFO error */ tmpu1b = rtl_read_byte(rtlpriv, REG_USB_AGG_TO); tmpu1b |= BIT(7); rtl_write_byte(rtlpriv, REG_USB_AGG_TO, tmpu1b); /* Fix 8051 ROM incorrect code operation */ rtl_write_byte(rtlpriv, REG_USB_MAGIC, USB_MAGIC_BIT7); /* To make sure that TxDMA can ready to download FW. */ /* We should reset TxDMA if IMEM RPT was not ready. */ do { tmpu1b = rtl_read_byte(rtlpriv, REG_TCR); if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE) break; msleep(20); } while (--tries); if (tries == 0) { RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", tmpu1b); tmpu1b = rtl_read_byte(rtlpriv, REG_CR); rtl_write_byte(rtlpriv, REG_CR, tmpu1b & (~TXDMA_EN)); msleep(20); /* Reset TxDMA */ rtl_write_byte(rtlpriv, REG_CR, tmpu1b | TXDMA_EN); } /* After MACIO reset,we must refresh LED state. */ if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS || ppsc->rfoff_reason == 0) { enum rf_pwrstate rfpwr_state_toset; struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw); struct rtl_led *pLed0 = &(usbpriv->ledctl.sw_led0); rfpwr_state_toset = rtl92s_rf_onoff_detect(hw); if (rfpwr_state_toset == ERFON) rtl92s_sw_led_on(hw, pLed0); } return 0; }