static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) { rtsx_pci_init_cmd(pcr); /* Configure GPIO as output */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); /* Reset ASPM state to default value */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); /* Switch LDO3318 source from DV33 to card_3v3 */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); /* LED shine disabled, set initial shine cycle period */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); /* Configure driving */ rts5249_fill_driving(pcr, OUTPUT_3V3); if (pcr->flags & PCR_REVERSE_SOCKET) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0); else rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00); return rtsx_pci_send_cmd(pcr, 100); }
static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) { struct rtsx_cr_option *option = &(pcr->option); rts5249_init_from_cfg(pcr); rts5249_init_from_hw(pcr); rtsx_pci_init_cmd(pcr); /* Rest L1SUB Config */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); /* Configure GPIO as output */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); /* Reset ASPM state to default value */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); /* Switch LDO3318 source from DV33 to card_3v3 */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); /* LED shine disabled, set initial shine cycle period */ rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); /* Configure driving */ rts5249_fill_driving(pcr, OUTPUT_3V3); if (pcr->flags & PCR_REVERSE_SOCKET) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); else rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); /* * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced * to drive low, and we forcibly request clock. */ if (option->force_clkreq_0) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); else rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); }
static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) { switch (voltage) { case OUTPUT_3V3: rtsx_pci_write_register(pcr, LDO_CONFIG2, LDO_D3318_MASK, LDO_D3318_33V); rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); break; case OUTPUT_1V8: rtsx_pci_write_register(pcr, LDO_CONFIG2, LDO_D3318_MASK, LDO_D3318_18V); rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8); break; default: return -EINVAL; } rtsx_pci_init_cmd(pcr); rts5249_fill_driving(pcr, voltage); return rtsx_pci_send_cmd(pcr, 100); }
static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) { int err; u16 append; switch (voltage) { case OUTPUT_3V3: err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, PHY_TUNE_VOLTAGE_3V3); if (err < 0) return err; break; case OUTPUT_1V8: append = PHY_TUNE_D18_1V8; if (CHK_PCI_PID(pcr, 0x5249)) { err = rtsx_pci_update_phy(pcr, PHY_BACR, PHY_BACR_BASIC_MASK, 0); if (err < 0) return err; append = PHY_TUNE_D18_1V7; } err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, append); if (err < 0) return err; break; default: pcr_dbg(pcr, "unknown output voltage %d\n", voltage); return -EINVAL; } /* set pad drive */ rtsx_pci_init_cmd(pcr); rts5249_fill_driving(pcr, voltage); return rtsx_pci_send_cmd(pcr, 100); }
static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) { int err; if (voltage == OUTPUT_3V3) { err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24); if (err < 0) return err; } else if (voltage == OUTPUT_1V8) { err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02); if (err < 0) return err; err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24); if (err < 0) return err; } else { return -EINVAL; } /* set pad drive */ rtsx_pci_init_cmd(pcr); rts5249_fill_driving(pcr, voltage); return rtsx_pci_send_cmd(pcr, 100); }