void rtl8812_sreset_linked_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u32 rx_dma_status = 0;
rx_dma_status = rtw_read32(padapter, REG_RXDMA_STATUS);
if (rx_dma_status != 0x00)
RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n", __FUNCTION__, rx_dma_status);
#if 0
u32 regc50, regc58, reg824, reg800;
regc50 = rtw_read32(padapter, 0xc50);
regc58 = rtw_read32(padapter, 0xc58);
reg824 = rtw_read32(padapter, 0x824);
reg800 = rtw_read32(padapter, 0x800);
if (((regc50 & 0xFFFFFF00) != 0x69543400) ||
((regc58 & 0xFFFFFF00) != 0x69543400) ||
(((reg824 & 0xFFFFFF00) != 0x00390000) && (((reg824 & 0xFFFFFF00) != 0x80390000))) ||
(((reg800 & 0xFFFFFF00) != 0x03040000) && ((reg800 & 0xFFFFFF00) != 0x83040000))) {
RTW_INFO("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtw_hal_sreset_reset(padapter);
}
#endif
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
void rtl8188e_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt )
{
u8 opmode,macid;
u16 mst_rpt = cpu_to_le16 (mstatus_rpt);
u32 reg_macid_no_link = REG_MACID_NO_LINK_0;
opmode = (u8) mst_rpt;
macid = (u8)(mst_rpt >> 8) ;
DBG_871X("### %s: MStatus=%x MACID=%d \n", __FUNCTION__,opmode,macid);
FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt);
if(macid > 31){
macid = macid-32;
reg_macid_no_link = REG_MACID_NO_LINK_1;
}
//Delete select macid (MACID 0~63) from queue list.
if(opmode == 1)// 1:connect
{
rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link) & (~BIT(macid))));
}
else//0: disconnect
{
rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link)|BIT(macid)));
}
}
void rtl8192c_sreset_linked_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtw_hal_sreset_reset(padapter);
}
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
void rtl8192c_sreset_linked_status_check(_adapter *padapter)
{
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
rtl8192c_silentreset_for_specific_platform(padapter);
}
}
static u8 _LLTRead(
IN PADAPTER Adapter,
IN u32 address
)
{
int count = 0;
u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
rtw_write32(Adapter, REG_LLT_INIT, value);
//polling and get value
do{
value = rtw_read32(Adapter, REG_LLT_INIT);
if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
return (u8)value;
}
if(count > POLLING_LLT_THRESHOLD){
//RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
break;
}
}while(count++);
return 0xFF;
}
//-------------------------------------------------------------------------
//
// LLT R/W/Init function
//
//-------------------------------------------------------------------------
static u8 _LLTWrite(
IN PADAPTER Adapter,
IN u32 address,
IN u32 data
)
{
u8 status = _SUCCESS;
int count = 0;
u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
rtw_write32(Adapter, REG_LLT_INIT, value);
//polling
do{
value = rtw_read32(Adapter, REG_LLT_INIT);
if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
break;
}
if(count > POLLING_LLT_THRESHOLD){
//RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address));
status = _FAIL;
break;
}
}while(count++);
return status;
}
void ips_enter(_adapter * padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
_enter_pwrlock(&pwrpriv->lock);
pwrpriv->bips_processing = _TRUE;
// syn ips_mode with request
pwrpriv->ips_mode = pwrpriv->ips_mode_req;
pwrpriv->ips_enter_cnts++;
DBG_8192C("==>ips_enter cnts:%d\n",pwrpriv->ips_enter_cnts);
if(rf_off == pwrpriv->change_rfpwrstate )
{
DBG_8192C("==>power_saving_ctrl_wk_hdl change rf to OFF...LED(0x%08x).... \n\n",rtw_read32(padapter,0x4c));
if(pwrpriv->ips_mode == IPS_LEVEL_2) {
u8 rf_type;
padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
pwrpriv->bkeepfwalive = ( rf_type == RF_1T1R )? _TRUE : _FALSE;//rtl8192cu cannot support IPS_Level2 ,must debug
}
rtw_ips_pwr_down(padapter);
pwrpriv->current_rfpwrstate = rf_off;
}
pwrpriv->bips_processing = _FALSE;
_exit_pwrlock(&pwrpriv->lock);
}
int proc_get_read_reg(struct seq_file *m, void *v)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if (proc_get_read_addr==0xeeeeeeee) {
DBG_871X_SEL_NL(m, "address not initialized\n");
return 0;
}
switch(proc_get_read_len)
{
case 1:
DBG_871X_SEL_NL(m, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));
break;
case 2:
DBG_871X_SEL_NL(m, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));
break;
case 4:
DBG_871X_SEL_NL(m, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));
break;
default:
DBG_871X_SEL_NL(m, "error read length=%d\n", proc_get_read_len);
break;
}
return 0;
}
static void fw_cmd_data(PADAPTER pAdapter, u32 *value, u8 flag)
{
if (flag == 0) // set
rtw_write32(pAdapter, IOCMD_DATA_REG, *value);
else // query
*value = rtw_read32(pAdapter, IOCMD_DATA_REG);
}
int _ips_leave(_adapter * padapter)
{
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
int result = _SUCCESS;
if ((pwrpriv->rf_pwrstate == rf_off) &&(!pwrpriv->bips_processing))
{
pwrpriv->bips_processing = true;
pwrpriv->change_rfpwrstate = rf_on;
pwrpriv->ips_leave_cnts++;
DBG_871X("==>ips_leave cnts:%d\n", pwrpriv->ips_leave_cnts);
if ((result = rtw_ips_pwr_up(padapter)) == _SUCCESS) {
pwrpriv->rf_pwrstate = rf_on;
}
DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n");
DBG_871X("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c));
pwrpriv->bips_processing = false;
pwrpriv->bkeepfwalive = false;
pwrpriv->bpower_saving = false;
}
return result;
}
//-------------------------------------------------------------------
//
// EEPROM/EFUSE Content Parsing
//
//-------------------------------------------------------------------
static VERSION_8192C
ReadChipVersion(
IN PADAPTER Adapter
)
{
u32 value32;
VERSION_8192C version;
u8 ChipVersion=0;
value32 = rtw_read32(Adapter, REG_SYS_CFG);
#if 0
if(value32 & TRP_VAUX_EN){
//Test chip
switch(((value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT))
{
case 0: //8191C
version = VERSION_TEST_CHIP_91C;
break;
case 1: //8188C
version = VERSION_TEST_CHIP_88C;
break;
default:
// TODO: set default to 1T1R?
RT_ASSERT(FALSE,("Chip Version can't be recognized.\n"));
break;
}
}
else{
int proc_get_read_reg(struct seq_file *m, void* data)
{
struct net_device *dev = m->private;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
if(proc_get_read_addr==0xeeeeeeee)
{
return 0;
}
switch(proc_get_read_len)
{
case 1:
seq_printf(m, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));
break;
case 2:
seq_printf(m, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));
break;
case 4:
seq_printf(m, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));
break;
default:
seq_printf(m, "error read length=%d\n", proc_get_read_len);
break;
}
return 0;
}
void rtl8188e_sreset_xmit_status_check(struct adapter *padapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
unsigned long current_time;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
unsigned int diff_time;
u32 txdma_status;
txdma_status = rtw_read32(padapter, REG_TXDMA_STATUS);
if (txdma_status != 0x00) {
DBG_88E("%s REG_TXDMA_STATUS:0x%08x\n", __func__, txdma_status);
rtw_write32(padapter, REG_TXDMA_STATUS, txdma_status);
rtl8188e_silentreset_for_specific_platform(padapter);
}
/* total xmit irp = 4 */
current_time = jiffies;
if (0 == pxmitpriv->free_xmitbuf_cnt) {
diff_time = jiffies_to_msecs(current_time - psrtpriv->last_tx_time);
if (diff_time > 2000) {
if (psrtpriv->last_tx_complete_time == 0) {
psrtpriv->last_tx_complete_time = current_time;
} else {
diff_time = jiffies_to_msecs(current_time - psrtpriv->last_tx_complete_time);
if (diff_time > 4000) {
DBG_88E("%s tx hang\n", __func__);
rtl8188e_silentreset_for_specific_platform(padapter);
}
}
}
}
}
//
// Description:
// Enalbe SDIO Host Interrupt Mask configuration on SDIO local domain.
//
// Assumption:
// 1. Using SDIO Local register ONLY for configuration.
// 2. PASSIVE LEVEL
//
// Created by Roger, 2011.02.11.
//
void EnableInterrupt8723BSdio(PADAPTER padapter)
{
PHAL_DATA_TYPE pHalData;
u32 himr;
#ifdef CONFIG_CONCURRENT_MODE
if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){
padapter = padapter->pbuddy_adapter;
}
#endif
pHalData = GET_HAL_DATA(padapter);
himr = cpu_to_le32(pHalData->sdio_himr);
sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8*)&himr);
RT_TRACE(_module_hci_ops_c_, _drv_notice_,
("%s: enable SDIO HIMR=0x%08X\n", __FUNCTION__, pHalData->sdio_himr));
// Update current system IMR settings
himr = rtw_read32(padapter, REG_HSIMR);
rtw_write32(padapter, REG_HSIMR, himr|pHalData->SysIntrMask);
RT_TRACE(_module_hci_ops_c_, _drv_notice_,
("%s: enable HSIMR=0x%08X\n", __FUNCTION__, pHalData->SysIntrMask));
//
// <Roger_Notes> There are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM.
// So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore.
// 2011.10.19.
//
rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
}
void ips_enter(_adapter * padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
_enter_pwrlock(&pwrpriv->lock);
pwrpriv->bips_processing = _TRUE;
// syn ips_mode with request
pwrpriv->ips_mode = pwrpriv->ips_mode_req;
pwrpriv->ips_enter_cnts++;
DBG_8192C("==>ips_enter cnts:%d\n",pwrpriv->ips_enter_cnts);
if(rf_off == pwrpriv->change_rfpwrstate )
{
DBG_8192C("==>power_saving_ctrl_wk_hdl change rf to OFF...LED(0x%08x).... \n\n",rtw_read32(padapter,0x4c));
if(pwrpriv->ips_mode == IPS_LEVEL_2)
pwrpriv->bkeepfwalive = _TRUE;
rtw_ips_pwr_down(padapter);
pwrpriv->rf_pwrstate = rf_off;
}
pwrpriv->bips_processing = _FALSE;
_exit_pwrlock(&pwrpriv->lock);
}
u8 rtl8192c_sreset_get_wifi_status(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u8 status = WIFI_STATUS_SUCCESS;
u32 val32 = 0;
_irqL irqL;
if(psrtpriv->silent_reset_inprogress == _TRUE)
{
return status;
}
val32 =rtw_read32(padapter,REG_TXDMA_STATUS);
if(val32==0xeaeaeaea){
psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST;
}
else if(val32!=0){
DBG_8192C("txdmastatu(%x)\n",val32);
psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR;
}
if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status)
{
DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status);
status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL)));
}
DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status);
//status restore
psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS;
return status;
}
//
// Description:
// Clear corresponding SDIO Host ISR interrupt service.
//
// Assumption:
// Using SDIO Local register ONLY for configuration.
//
// Created by Roger, 2011.02.11.
//
void ClearInterrupt8723ASdio(PADAPTER padapter)
{
u32 tmp = 0;
tmp = rtw_read32(padapter, SPI_LOCAL_OFFSET | SDIO_REG_HISR);
rtw_write32(padapter, SPI_LOCAL_OFFSET|SDIO_REG_HISR, tmp);
// padapter->IsrContent.IntArray[0] = 0;
padapter->IsrContent = 0;
}
void
ODM_EdcaTurboInit(
IN void * pDM_VOID)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
Adapter->recvpriv.bIsAnyNonBEPkts =false;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",rtw_read32(pDM_Odm->Adapter,ODM_EDCA_VO_PARAM)));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",rtw_read32(pDM_Odm->Adapter,ODM_EDCA_VI_PARAM)));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",rtw_read32(pDM_Odm->Adapter,ODM_EDCA_BE_PARAM)));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",rtw_read32(pDM_Odm->Adapter,ODM_EDCA_BK_PARAM)));
} // ODM_InitEdcaTurbo
void DisableInterruptButCpwm28723ASdio(PADAPTER padapter)
{
u32 himr, tmp;
#ifdef CONFIG_CONCURRENT_MODE
if ((padapter->isprimary == _FALSE) && padapter->pbuddy_adapter){
padapter = padapter->pbuddy_adapter;
}
#endif
tmp = rtw_read32(padapter, SDIO_LOCAL_BASE | SDIO_REG_HIMR);
DBG_871X("DisableInterruptButCpwm28723ASdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
himr = cpu_to_le32(SPI_HIMR_DISABLED) | SPI_HISR_CPWM2;
rtw_write32(padapter, SPI_LOCAL_OFFSET | SDIO_REG_HIMR, himr);
tmp = rtw_read32(padapter, SPI_LOCAL_OFFSET | SDIO_REG_HIMR);
DBG_871X("DisableInterruptButCpwm28723ASdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
}
void TDLS_restore_workitem_callback(struct work_struct *work)
{
struct mlme_ext_priv*pmlmeext = container_of(work, struct mlme_ext_priv, TDLS_restore_workitem);
_adapter *padapter = pmlmeext->padapter;
u32 bit_6=1<<6;
rtw_write32(padapter, 0x0608, rtw_read32(padapter, 0x0608)|(bit_6));
DBG_8192C("wirte 0x0608, set bit6 on\n");
}
static VOID
_InitHardwareDropIncorrectBulkOut(
IN PADAPTER Adapter
)
{
u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
value32 |= DROP_DATA_EN;
rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
}
void rtl8188e_sreset_linked_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u32 rx_dma_status = 0;
u8 fw_status=0;
rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
if(rx_dma_status!= 0x00){
DBG_8192C("%s REG_RXDMA_STATUS:0x%08x \n",__FUNCTION__,rx_dma_status);
rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status);
}
fw_status = rtw_read8(padapter,REG_FMETHR);
if(fw_status != 0x00)
{
if(fw_status == 1)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Read_Efuse_Fail !! \n",__FUNCTION__,fw_status);
else if(fw_status == 2)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__FUNCTION__,fw_status);
}
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtw_hal_sreset_reset(padapter);
}
#endif
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
void rtl8723b_sreset_linked_status_check(_adapter *padapter)
{
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtl8723b_silentreset_for_specific_platform(padapter);
}
#endif
}
inline u8 rtl8821c_rcr_get(PADAPTER p, u32 *rcr)
{
u32 v32;
v32 = rtw_read32(p, REG_RCR_8821C);
if (rcr)
*rcr = v32;
GET_HAL_DATA(p)->ReceiveConfig = v32;
return _TRUE;
}
void rtl8723b_sreset_xmit_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
unsigned long current_time;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
unsigned int diff_time;
u32 txdma_status;
txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS);
if( txdma_status !=0x00 && txdma_status !=0xeaeaeaea){
DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
rtw_hal_sreset_reset(padapter);
}
#ifdef CONFIG_USB_HCI
//total xmit irp = 4
//DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
//if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
current_time = rtw_get_current_time();
if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
if (diff_time > 2000) {
if (psrtpriv->last_tx_complete_time == 0) {
psrtpriv->last_tx_complete_time = current_time;
}
else{
diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
if (diff_time > 4000) {
u32 ability = 0;
//padapter->Wifi_Error_Status = WIFI_TX_HANG;
ability = rtw_phydm_ability_get(padapter);
DBG_871X("%s tx hang %s\n", __FUNCTION__,
(ability & ODM_BB_ADAPTIVITY)? "ODM_BB_ADAPTIVITY" : "");
if (!(ability & ODM_BB_ADAPTIVITY))
rtw_hal_sreset_reset(padapter);
}
}
}
}
#endif // #ifdef CONFIG_USB_HCI
if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
inline u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter)
{
int err;
/*ack for xmit mgmt frames.*/
err = rtw_write32(adapter, REG_FWHW_TXQ_CTRL_8821C, rtw_read32(adapter, REG_FWHW_TXQ_CTRL_8821C) | BIT(12));
if (err == _FAIL)
return _FAIL;
return _SUCCESS;
}
int ips_leave(struct rtw_adapter *padapter)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct security_priv *psecuritypriv = &(padapter->securitypriv);
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
int result = _SUCCESS;
int keyid;
_enter_pwrlock(&pwrpriv->lock);
if ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) {
pwrpriv->bips_processing = true;
pwrpriv->change_rfpwrstate = rf_on;
pwrpriv->ips_leave_cnts++;
DBG_8192D("==>ips_leave cnts:%d\n", pwrpriv->ips_leave_cnts);
result = rtw_ips_pwr_up(padapter);
if (result == _SUCCESS)
pwrpriv->rf_pwrstate = rf_on;
if ((_WEP40_ == psecuritypriv->dot11PrivacyAlgrthm) ||
(_WEP104_ == psecuritypriv->dot11PrivacyAlgrthm)) {
DBG_8192D("==>%s,channel(%d),processing(%x)\n",
__func__, padapter->mlmeextpriv.cur_channel,
pwrpriv->bips_processing);
set_channel_bwmode(padapter,
padapter->mlmeextpriv.cur_channel,
HAL_PRIME_CHNL_OFFSET_DONT_CARE,
HT_CHANNEL_WIDTH_20);
for (keyid = 0; keyid < 4; keyid++) {
if (pmlmepriv->key_mask & BIT(keyid)) {
if (keyid ==
psecuritypriv->dot11PrivacyKeyIndex)
result =
rtw_set_key(padapter,
psecuritypriv,
keyid, 1);
else
result =
rtw_set_key(padapter,
psecuritypriv,
keyid, 0);
}
}
}
DBG_8192D("==> ips_leave.....LED(0x%08x)...\n",
rtw_read32(padapter, 0x4c));
pwrpriv->bips_processing = false;
pwrpriv->bkeepfwalive = false;
}
_exit_pwrlock(&pwrpriv->lock);
return result;
}
static void _dbg_dump_macreg(_adapter *padapter)
{
u32 offset = 0;
u32 val32 = 0;
u32 index =0 ;
for(index=0;index<64;index++)
{
offset = index*4;
val32 = rtw_read32(padapter,offset);
DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
}
}
static int _FWFreeToGo(
IN PADAPTER Adapter
)
{
u32 counter = 0;
u32 value32;
// polling CheckSum report
do{
value32 = rtw_read32(Adapter, REG_MCUFWDL);
}while((counter ++ < POLLING_READY_TIMEOUT_COUNT) && (!(value32 & FWDL_ChkSum_rpt)));
if(counter >= POLLING_READY_TIMEOUT_COUNT){
DBG_8192C("chksum report faill ! REG_MCUFWDL:0x%08x .\n",value32);
return _FAIL;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n",value32));
value32 = rtw_read32(Adapter, REG_MCUFWDL);
value32 |= MCUFWDL_RDY;
value32 &= ~WINTINI_RDY;
rtw_write32(Adapter, REG_MCUFWDL, value32);
// polling for FW ready
counter = 0;
do
{
if(rtw_read32(Adapter, REG_MCUFWDL) & WINTINI_RDY){
//RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",PlatformIORead4Byte(Adapter, REG_MCUFWDL)) );
return _SUCCESS;
}
rtw_mdelay_os(5);
}while(counter++ < POLLING_READY_TIMEOUT_COUNT);
DBG_8192C("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n",rtw_read32(Adapter, REG_MCUFWDL));
return _FAIL;
}
static void _dbg_dump_macreg(PADAPTER padapter)
{
u32 offset = 0;
u32 val32 = 0;
u32 index = 0;
for (index = 0; index < 64; index++) {
offset = index * 4;
val32 = rtw_read32(padapter, offset);
/* RTW_INFO("offset : 0x%02x ,val:0x%08x\n", offset, val32); */
RTW_INFO("offset : 0x%02x ,val:0x%08x\n", offset, val32);
}
}
