static void
rtwn_usb_drop_incorrect_tx(struct rtwn_softc *sc)
{
rtwn_setbits_1_shift(sc, R92C_TXDMA_OFFSET_CHK, 0,
R92C_TXDMA_OFFSET_DROP_DATA_EN, 1);
}
void
r92c_fw_download_enable(struct rtwn_softc *sc, int enable)
{
if (enable) {
/* 8051 enable. */
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, 0,
R92C_SYS_FUNC_EN_CPUEN, 1);
/* MCU firmware download enable. */
rtwn_setbits_1(sc, R92C_MCUFWDL, 0, R92C_MCUFWDL_EN);
/* 8051 reset. */
rtwn_setbits_1_shift(sc, R92C_MCUFWDL, R92C_MCUFWDL_ROM_DLEN,
0, 2);
} else {
/* MCU download disable. */
rtwn_setbits_1(sc, R92C_MCUFWDL, R92C_MCUFWDL_EN, 0);
/* Reserved for f/w extension. */
rtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
}
}
void
r92c_fw_reset(struct rtwn_softc *sc, int reason)
{
int ntries;
if (reason == RTWN_FW_RESET_CHECKSUM)
return;
/* Tell 8051 to reset itself. */
rtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
/* Wait until 8051 resets by itself. */
for (ntries = 0; ntries < 100; ntries++) {
if ((rtwn_read_2(sc, R92C_SYS_FUNC_EN) &
R92C_SYS_FUNC_EN_CPUEN) == 0)
return;
rtwn_delay(sc, 50);
}
/* Force 8051 reset. */
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_CPUEN, 0, 1);
}
int
r92cu_power_on(struct rtwn_softc *sc)
{
#define RTWN_CHK(res) do { \
if (res != 0) \
return (EIO); \
} while(0)
uint32_t reg;
int ntries;
/* Wait for autoload done bit. */
for (ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for chip autoload\n");
return (ETIMEDOUT);
}
/* Unlock ISO/CLK/Power control register. */
RTWN_CHK(rtwn_write_1(sc, R92C_RSV_CTRL, 0));
/* Move SPS into PWM mode. */
RTWN_CHK(rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b));
/* just in case if power_off() was not properly executed. */
rtwn_delay(sc, 100);
reg = rtwn_read_1(sc, R92C_LDOV12D_CTRL);
if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
RTWN_CHK(rtwn_write_1(sc, R92C_LDOV12D_CTRL,
reg | R92C_LDOV12D_CTRL_LDV12_EN));
rtwn_delay(sc, 100);
RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
R92C_SYS_ISO_CTRL_MD2PP, 0));
}
/* Auto enable WLAN. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
R92C_APS_FSMCO_APFM_ONMAC, 1));
for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for MAC auto ON\n");
return (ETIMEDOUT);
}
/* Enable radio, GPIO and LED functions. */
RTWN_CHK(rtwn_write_2(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS |
R92C_APS_FSMCO_PDN_EN |
R92C_APS_FSMCO_PFM_ALDN));
/* Release RF digital isolation. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_ISO_CTRL,
R92C_SYS_ISO_CTRL_DIOR, 0, 1));
/* Initialize MAC. */
RTWN_CHK(rtwn_setbits_1(sc, R92C_APSD_CTRL,
R92C_APSD_CTRL_OFF, 0));
for (ntries = 0; ntries < 1000; ntries++) {
if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
R92C_APSD_CTRL_OFF_STATUS))
break;
rtwn_delay(sc, 50);
}
if (ntries == 1000) {
device_printf(sc->sc_dev,
"timeout waiting for MAC initialization\n");
return (ETIMEDOUT);
}
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
R92C_CR_CALTMR_EN));
RTWN_CHK(rtwn_write_1(sc, 0xfe10, 0x19));
return (0);
#undef RTWN_CHK
}
void
r12a_power_off(struct rtwn_softc *sc)
{
struct r12a_softc *rs = sc->sc_priv;
int error, ntries;
/* Stop Rx. */
error = rtwn_write_1(sc, R92C_CR, 0);
if (error == ENXIO) /* hardware gone */
return;
/* Move card to Low Power state. */
/* Block all Tx queues. */
rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
for (ntries = 0; ntries < 10; ntries++) {
/* Should be zero if no packet is transmitting. */
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
break;
rtwn_delay(sc, 5000);
}
if (ntries == 10) {
device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
__func__);
return;
}
/* Turn off 3-wire. */
rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
/* CCK and OFDM are disabled, and clock are gated. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_delay(sc, 1);
/* Reset whole BB. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
/* Reset MAC TRX. */
rtwn_write_1(sc, R92C_CR,
R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN);
/* check if removed later. (?) */
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
/* Respond TxOK to scheduler */
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
/* If firmware in ram code, do reset. */
#ifndef RTWN_WITHOUT_UCODE
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
r12a_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
#endif
/* Reset MCU. */
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
0, 1);
rtwn_write_1(sc, R92C_MCUFWDL, 0);
/* Move card to Disabled state. */
/* Turn off 3-wire. */
rtwn_write_1(sc, R12A_HSSI_PARAM1(0), 0x04);
rtwn_write_1(sc, R12A_HSSI_PARAM1(1), 0x04);
/* Reset BB, close RF. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
rtwn_delay(sc, 1);
/* SPS PWM mode. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
R92C_APS_FSMCO_SOP_RCK | R92C_APS_FSMCO_SOP_ABG, 3);
/* ANA clock = 500k. */
rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
/* Turn off MAC by HW state machine */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
1);
for (ntries = 0; ntries < 10; ntries++) {
/* Wait until it will be disabled. */
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_OFF) == 0)
break;
rtwn_delay(sc, 5000);
}
if (ntries == 10) {
device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
__func__);
return;
}
/* Reset 8051. */
rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_CPUEN,
0, 1);
/* Fill the default value of host_CPU handshake field. */
rtwn_write_1(sc, R92C_MCUFWDL,
R92C_MCUFWDL_EN | R92C_MCUFWDL_CHKSUM_RPT);
rtwn_setbits_1(sc, R92C_GPIO_IO_SEL, 0xf0, 0xc0);
/* GPIO 11 input mode, 10...8 output mode. */
rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x07);
/* GPIO 7...0, output = input */
rtwn_write_1(sc, R92C_GPIO_OUT, 0);
/* GPIO 7...0 output mode. */
rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
rtwn_write_1(sc, R92C_GPIO_MOD, 0);
/* Turn on ZCD. */
rtwn_setbits_2(sc, 0x014, 0, 0x0180);
/* Force PFM mode. */
rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0x01, 0);
/* LDO sleep mode. */
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
/* ANA clock = 500k. */
rtwn_setbits_1(sc, R92C_SYS_CLKR, R92C_SYS_CLKR_ANA8M, 0);
/* SOP option to disable BG/MB. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
R92C_APS_FSMCO_SOP_RCK, 3);
/* Disable RFC_0. */
rtwn_setbits_1(sc, R92C_RF_CTRL, R92C_RF_CTRL_RSTB, 0);
/* Disable RFC_1. */
rtwn_setbits_1(sc, R12A_RF_B_CTRL, R92C_RF_CTRL_RSTB, 0);
/* Enable WL suspend. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS,
1);
rs->rs_flags &= ~R12A_IQK_RUNNING;
}
int
r12a_power_on(struct rtwn_softc *sc)
{
#define RTWN_CHK(res) do { \
if (res != 0) \
return (EIO); \
} while(0)
int ntries;
r12a_rf_init_workaround(sc);
/* Force PWM mode. */
RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01));
/* Turn off ZCD. */
RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0));
/* Enable LDO normal mode. */
RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP,
0));
/* GPIO 0...7 input mode. */
RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0));
/* GPIO 11...8 input mode. */
RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0));
/* Enable WL suspend. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
/* Enable 8051. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
0, R92C_SYS_FUNC_EN_CPUEN, 1));
/* Disable SW LPS. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_APFM_RSM, 0, 1));
/* Wait for power ready bit. */
for (ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for chip power up\n");
return (ETIMEDOUT);
}
/* Disable WL suspend. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
R92C_APS_FSMCO_APFM_ONMAC, 1));
for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000)
return (ETIMEDOUT);
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
R92C_CR_CALTMR_EN));
return (0);
}
void
r88eu_power_off(struct rtwn_softc *sc)
{
uint8_t reg;
int error, ntries;
/* Disable any kind of TX reports. */
error = rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
if (error == ENXIO) /* hardware gone */
return;
/* Stop Rx. */
rtwn_write_1(sc, R92C_CR, 0);
/* Move card to Low Power State. */
/* Block all Tx queues. */
rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
for (ntries = 0; ntries < 10; ntries++) {
/* Should be zero if no packet is transmitting. */
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
break;
rtwn_delay(sc, 5000);
}
if (ntries == 10) {
device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
__func__);
return;
}
/* CCK and OFDM are disabled, and clock are gated. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_delay(sc, 1);
/* Reset MAC TRX */
rtwn_write_1(sc, R92C_CR,
R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
/* check if removed later */
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
/* Respond TxOK to scheduler */
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
/* If firmware in ram code, do reset. */
#ifndef RTWN_WITHOUT_UCODE
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
#endif
/* Reset MCU ready status. */
rtwn_write_1(sc, R92C_MCUFWDL, 0);
/* Disable 32k. */
rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
/* Move card to Disabled state. */
/* Turn off RF. */
rtwn_write_1(sc, R92C_RF_CTRL, 0);
/* LDO Sleep mode. */
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
/* Turn off MAC by HW state machine */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
R92C_APS_FSMCO_APFM_OFF, 1);
for (ntries = 0; ntries < 10; ntries++) {
/* Wait until it will be disabled. */
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_OFF) == 0)
break;
rtwn_delay(sc, 5000);
}
if (ntries == 10) {
device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
__func__);
return;
}
/* schmit trigger */
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
/* Enable WL suspend. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_PCIE, R92C_APS_FSMCO_AFSM_HSUS, 1);
/* Enable bandgap mbias in suspend. */
rtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
/* Clear SIC_EN register. */
rtwn_setbits_1(sc, R92C_GPIO_MUXCFG + 1, 0x10, 0);
/* Set USB suspend enable local register */
rtwn_setbits_1(sc, R92C_USB_SUSPEND, 0, 0x10);
/* Reset MCU IO Wrapper. */
reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
/* marked as 'For Power Consumption' code. */
rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
rtwn_write_1(sc, R92C_GPIO_IO_SEL,
rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
/* Set LNA, TRSW, EX_PA Pin to output mode. */
rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
}
int
r88ee_power_on(struct rtwn_softc *sc)
{
int ntries;
/* Disable XTAL output for power saving. */
rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
/* Unlock ISO/CLK/Power control register. */
rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
rtwn_write_1(sc, R92C_RSV_CTRL, 0);
/* Wait for power ready bit */
for(ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for chip power up\n");
return (ETIMEDOUT);
}
/* Reset BB. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
/* schmit trigger */
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
/* Disable HWPDN. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_APDM_HPDN, 0, 1);
/* Disable WL suspend. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
/* Auto-enable WLAN */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
0, R92C_APS_FSMCO_APFM_ONMAC, 1);
for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000)
return (ETIMEDOUT);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
/* Enable LDO normal mode. */
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
rtwn_write_2(sc, R92C_CR, 0);
rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
R92C_CR_CALTMR_EN);
rtwn_write_4(sc, R92C_INT_MIG, 0);
rtwn_write_4(sc, R92C_MCUTST_1, 0);
return (0);
}
