コード例 #1
0
void __bare_init at91sam926x_sdramc_init(struct at91sam926x_lowlevel_cfg *cfg)
{
	u32 r;
	int i;
	int in_sram = running_in_sram();

	/*
	 * SDRAMC Check if Refresh Timer Counter is already initialized
	 */
	r = at91_sdramc_read(AT91_SDRAMC_TR);
	if (r && !in_sram)
		return;

	/* SDRAMC_MR : Normal Mode */
	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);

	/* SDRAMC_TR - Refresh Timer register */
	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr1);

	/* SDRAMC_CR - Configuration register*/
	at91_sdramc_write(AT91_SDRAMC_CR, cfg->sdrc_cr);

	/* Memory Device Type */
	at91_sdramc_write(AT91_SDRAMC_MDR, cfg->sdrc_mdr);

	/* SDRAMC_MR : Precharge All */
	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_MR : refresh */
	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);

	/* access SDRAM 8 times */
	for (i = 0; i < 8; i++)
		access_sdram();

	/* SDRAMC_MR : Load Mode Register */
	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_MR : Normal Mode */
	at91_sdramc_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_TR : Refresh Timer Counter */
	at91_sdramc_write(AT91_SDRAMC_TR, cfg->sdrc_tr2);

	/* access SDRAM */
	access_sdram();
}
コード例 #2
0
ファイル: mem.c プロジェクト: 12thmantec/u-boot-novena-spl
/*********************************************************************************
 * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
 *   -- called from SRAM, or Flash (using temp SRAM stack).
 *********************************************************************************/
void prcm_init(void)
{
	u32 div;
	void (*f_lock_pll) (u32, u32, u32, u32);
	extern void *_end_vect, *_start;

	f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);

	__raw_writel(0, CM_FCLKEN1_CORE);	   /* stop all clocks to reduce ringing */
	__raw_writel(0, CM_FCLKEN2_CORE);	   /* may not be necessary */
	__raw_writel(0, CM_ICLKEN1_CORE);
	__raw_writel(0, CM_ICLKEN2_CORE);

	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */
	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */
	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */
	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */

	div = BUS_DIV;
	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
	sdelay(1000);

	if(running_in_sram()){
		/* If running fully from SRAM this is OK.  The Flash bus drops out for just a little.
		* but then comes back.  If running from Flash this sequence kills you, thus you need
		* to run it using CONFIG_PARTIAL_SRAM.
		*/
		__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
		wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
		sdelay(1000);
		/* set clock selection and dpll dividers. */
		__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);	 /* set pll for target rate */
		__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
		sdelay(10000);
		__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
		sdelay(10000);
		wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY);  /*wait for dpll lock */
	}else if(running_in_flash()){
		/* if running from flash, need to jump to small relocated code area in SRAM.
		 * This is the only safe spot to do configurations from.
		 */
		(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
	}

	__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL);   /* enable apll */
	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */
	sdelay(1000);
}
コード例 #3
0
void __bare_init at91sam926x_lowlevel_init(struct at91sam926x_lowlevel_cfg *cfg)
{
	u32 r;
	int in_sram = running_in_sram();

	at91sam926x_lowlevel_board_config(cfg);

	__raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);

	/* configure PIOx as EBI0 D[16-31] */
	at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
	at91_mux_set_pullup(cfg->pio, cfg->ebi_pio_ppudr, true);
	if (cfg->ebi_pio_is_peripha)
		at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr);

	at91_sys_write(cfg->matrix_csa, cfg->ebi_csa);

	/* flash */
	at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode);

	at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle);

	at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse);

	at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);

	/*
	 * PMC Check if the PLL is already initialized
	 */
	r = at91_pmc_read(AT91_PMC_MCKR);
	if (r & AT91_PMC_CSS && !in_sram)
		return;

	/*
	 * Enable the Main Oscillator
	 */
	at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor);

	do {
		r = at91_pmc_read(AT91_PMC_SR);
	} while (!(r & AT91_PMC_MOSCS));

	/*
	 * PLLAR: x MHz for PCK
	 */
	at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar);

	do {
		r = at91_pmc_read(AT91_PMC_SR);
	} while (!(r & AT91_PMC_LOCKA));

	/*
	 * PCK/x = MCK Master Clock from SLOW
	 */
	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1);

	pmc_check_mckrdy();

	/*
	 * PCK/x = MCK Master Clock from PLLA
	 */
	at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2);

	pmc_check_mckrdy();

	/*
	 * Init SDRAM
	 */
	at91sam926x_sdramc_init(cfg);

	/* User reset enable*/
	at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);

#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
	/* MATRIX_MCFG - REMAP all masters */
	at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
#endif
	/*
	 * When boot from external boot
	 * we need to enable mck and ohter clock
	 * so enable all of them
	 * We will shutdown what we don't need later
	 */
	at91_pmc_write(AT91_PMC_PCER, 0xffffffff);
}
コード例 #4
0
ファイル: clock_omap3430.c プロジェクト: XVilka/2ndboot-ng
/******************************************************************************
 * prcm_init() - inits clocks for PRCM as defined in clocks.h
 *   -- called from SRAM, or Flash (using temp SRAM stack).
 *****************************************************************************/
void prcm_init(void)
{
	void (*f_lock_pll) (u32, u32, u32, u32);
	int xip_safe, p0, p1, p2, p3;
	u32 osc_clk=0, sys_clkin_sel;
	extern void *_end_vect, *_start;
	u32 clk_index, sil_index=1;
	dpll_param *dpll_param_p;

	f_lock_pll =
	    (void *)((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE);

	xip_safe = running_in_sram();
#ifdef CONFIG_3430VIRTIO
	xip_safe = 1;
#endif
	/* Gauge the input clock speed and find out the sys_clkin_sel
	 * value corresponding to the input clock.
	 */
	osc_clk = get_osc_clk_speed();
	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
	
	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */

	sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
	clk_index = sys_clkin_sel;

	sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */

	sil_index = get_silindex();

	/* Unlock MPU DPLL (slows things down, and needed later) */
	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
	wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);

	/* Getting the base address of Core DPLL param table*/
	dpll_param_p = (dpll_param *)get_core_dpll_param();
	/* Moving it to the right sysclk and ES rev base */
	dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
	if(xip_safe){
		/* CORE DPLL */
		/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
		sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
		wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
		/* For 3430 ES1.0 Errata 1.50, default value directly doesnt
		   work. write another value and then default value. */
		sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);	/* m3x2 */
		sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);		/* m3x2 */
		sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);	/* Set M2 */
		sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);	/* Set M */
		sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n);	/* Set N */
		sr32(CM_CLKSEL1_PLL, 6, 1, 0);			/* 96M Src */
		sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);	/* ssi */
		sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);	/* fsusb ES1 only */
		sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);	/* l4 */
		sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV);	/* l3 */
		sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);		/* gfx */
		sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);		/* reset mgr */
#ifndef CONFIG_OMAP36XX
		sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
#endif
		sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);		/* lock mode */
		wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
	} else if(running_in_flash()){
		/* if running from flash, jump to small relocated code area in SRAM.*/
		p0 = __raw_readl(CM_CLKEN_PLL);
		sr32((u32)&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
#ifndef CONFIG_OMAP36XX
		sr32((u32)&p0, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
#endif

		p1 = __raw_readl(CM_CLKSEL1_PLL);
		sr32((u32)&p1, 27, 2, dpll_param_p->m2);	/* Set M2 */
		sr32((u32)&p1, 16, 11, dpll_param_p->m);	/* Set M */
		sr32((u32)&p1, 8, 7, dpll_param_p->n);		/* Set N */
		sr32((u32)&p1, 6, 1, 0);		/* set source for 96M */
		p2 = __raw_readl(CM_CLKSEL_CORE);
		sr32((u32)&p2, 8, 4, CORE_SSI_DIV);	/* ssi */
		sr32((u32)&p2, 4, 2, CORE_FUSB_DIV);	/* fsusb ES1 only*/
		sr32((u32)&p2, 2, 2, CORE_L4_DIV);	/* l4 */
		sr32((u32)&p2, 0, 2, CORE_L3_DIV);	/* l3 */

		p3 = CM_IDLEST_CKGEN;

		(*f_lock_pll) (p0, p1, p2, p3);
	}

#ifdef CONFIG_OMAP36XX
	per_dpll_init_36XX(clk_index);
	iva_dpll_init_36XX(clk_index, sil_index);
	mpu_dpll_init_36XX(clk_index, sil_index);
#else
	per_dpll_init_34XX(clk_index);
	iva_dpll_init_34XX(clk_index, sil_index);
	mpu_dpll_init_34XX(clk_index, sil_index);
#endif

	/* Set up GPTimers to sys_clk source only */
 	sr32(CM_CLKSEL_PER, 0, 8, 0xff);
	sr32(CM_CLKSEL_WKUP, 0, 1, 1);

	sdelay(5000);
}