void __init s3c2443_init_clocks(int xtal) { unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); int ptr; clk_epll.rate = s3c2443_get_epll(epllcon, xtal); clk_epll.parent = &clk_epllref.clk; s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, armdiv, ARRAY_SIZE(armdiv), S3C2443_CLKDIV0_ARMDIV_MASK); s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_register_clksrc(clksrcs[ptr], 1); /* We must be careful disabling the clocks we are not intending to * be using at boot time, as subsystems such as the LCD which do * their own DMA requests to the bus can cause the system to lockup * if they where in the middle of requesting bus access. * * Disabling the LCD clock if the LCD is active is very dangerous, * and therefore the bootloader should be careful to not enable * the LCD clock if it is not needed. */ /* install (and disable) the clocks we do not need immediately */ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); s3c_pwmclk_init(); }
void __init s3c2416_init_clocks(int xtal) { u32 epllcon = __raw_readl(S3C2443_EPLLCON); u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4); int ptr; /* s3c2416 EPLL compatible with s3c64xx */ clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1); clk_epll.parent = &clk_epllref.clk; s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div); for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_register_clksrc(clksrcs[ptr], 1); s3c_pwmclk_init(); }
void __init s3c2416_init_clocks(int xtal) { u32 epllcon = __raw_readl(S3C2443_EPLLCON); u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4); int ptr; /* s3c2416 EPLL compatible with s3c64xx */ clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1); clk_epll.parent = &clk_epllref.clk; s3c2443_common_init_clocks(xtal, s3c2416_get_pll, armdiv, ARRAY_SIZE(armdiv), S3C2416_CLKDIV0_ARMDIV_MASK); for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_register_clksrc(clksrcs[ptr], 1); s3c24xx_register_clock(&hsmmc0_clk); clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); s3c_pwmclk_init(); }