int timer_init(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); ulong tmr; /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ writel(0x0f00, &timers->TCFG0); if (timer_load_val == 0) { /* * for 10 ms clock period @ PCLK with 4 bit divider = 1/2 * (default) and prescaler = 16. Should be 10390 * @33.25MHz and 15625 @ 50 MHz */ timer_load_val = get_PCLK() / (2 * 16 * 100); timer_clk = get_PCLK() / (2 * 16); } /* load value for 10 ms timeout */ lastdec = timer_load_val; writel(timer_load_val, &timers->TCNTB4); /* auto load, manual update of Timer 4 */ tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000; writel(tmr, &timers->TCON); /* auto load, start Timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; writel(tmr, &timers->TCON); timestamp = 0; return (0); }
int timer_init(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); ulong tmr; /* use PWM Timer 4 because it has no output */ /* prescaler for Timer 4 is 16 */ writel(0x0f00, &timers->tcfg0); gd->timer_rate_hz = get_PCLK() /(2*16*100); gd->tbl = get_PCLK() / (2 * 16); /* load value for 10 ms timeout */ gd->lastinc = gd->timer_rate_hz; writel(gd->timer_rate_hz, &timers->tcntb4); /* auto load, manual update of timer 4 */ tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; writel(tmr, &timers->tcon); /* auto load, start timer 4 */ tmr = (tmr & ~0x0700000) | 0x0500000; writel(tmr, &timers->tcon); gd->timer_reset_value = 0; return (0); }
/* macro to read the 16 bit timer */ static inline ulong READ_TIMER(void) { struct s3c24x0_timers *timers = s3c24x0_get_base_timers(); return readl(&timers->TCNTO4) & 0xffff; }